公开(公告)号：EP1052693A2

公开(公告)日：2000-11-15

申请号：EP00303901.3

申请日：2000-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Morgan, Eric G. ,  Vandenbossche, Eric ,  Singhal, Piyush M.

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.

公开(公告)号：EP1052693A3

公开(公告)日：2003-08-13

申请号：EP00303901.3

申请日：2000-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Morgan, Eric G. ,  Vandenbossche, Eric ,  Singhal, Piyush M.

IPC: H01L21/762

CPC classification number: H01L21/76224

Abstract: An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.

Abstract translation: IC隔离结构包括设置在具有表面部分的导电层中的凹部。 凹部具有与表面部分相邻的侧壁，并且隔离结构还包括设置在凹部中并与表面部分重叠的绝缘体。 因此，如果晶体管设置在与凹槽侧壁相邻的导电层中，则绝缘体的重叠部分增加了上凹部角部和栅电极之间的距离。 这种增加的距离将驼峰效应降低到可容忍的水平。

公开(公告)号：EP1720170B1

公开(公告)日：2008-11-26

申请号：EP06252214.9

申请日：2006-04-25

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics SA ,  STMicroelectronics S.r.l.

Inventor： Alini, Roberto ,  Rovati, Sergio Stefano ,  Vandenbossche, Eric ,  Paskins, Christopher

IPC: G11C17/16

CPC classification number: G11C17/16

公开(公告)号：EP1720170A1

公开(公告)日：2006-11-08

申请号：EP06252214.9

申请日：2006-04-25

Applicant: STMicroelectronics, Inc.

Inventor： Alini, Roberto ,  Rovati, Sergio Stefano ,  Vandenbossche, Eric ,  Paskins, Christopher

IPC: G11C17/16

CPC classification number: G11C17/16

Abstract: A one-time programmable circuit uses forced BJT h FE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.

Abstract translation: 一次性可编程电路使用强制BJTħFE降解成数字信息永久地存储为逻辑零或逻辑一的状态。 强制降解是通过施加电压或电流到BJT为特定时间的反向偏置基极 - 发射极结，使结的显著降解而不破坏它来实现的。