公开(公告)号：EP1777535A3

公开(公告)日：2007-10-31

申请号：EP06255109.8

申请日：2006-10-03

Applicant: STMicroelectronics, Inc. ,  STMICROELECTRONICS SA

Inventor： Fruhauf, Serge F. ,  Pomet, Alain C.

IPC: G01R31/317 ,  G06K19/073

CPC classification number: G01R31/31719 ,  G06K19/07309

Abstract: An apparatus includes a plurality of macrocells (402-406) formed from logic capable of performing one or more functions. The apparatus also includes a clock tree (408) capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch (410-414) within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting (418) a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

公开(公告)号：EP1772811A3

公开(公告)日：2007-07-25

申请号：EP06255105.6

申请日：2006-10-03

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics SA

Inventor： Fruhauf, Serge F. ,  Pomet, Alain C.

IPC: G06F21/02 ,  G06F21/00

CPC classification number: H04L9/003 ,  G06F21/755 ,  G06F21/77 ,  G06F2221/2123 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.

公开(公告)号：EP1480162B1

公开(公告)日：2006-05-17

申请号：EP04252530.3

申请日：2004-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Fruhauf, Serge ,  Leaming, Taylor J. ,  Pomet, Alain C.

IPC: G06K19/07 ,  G06K7/00

CPC classification number: G06K7/10465 ,  G06K7/0008 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07733

公开(公告)号：EP1480162A1

公开(公告)日：2004-11-24

申请号：EP04252530.3

申请日：2004-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Fruhauf, Serge ,  Leaming, Taylor J. ,  Pomet, Alain C.

IPC: G06K19/07 ,  G06K7/00

CPC classification number: G06K7/10465 ,  G06K7/0008 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07733

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

Abstract translation: 用于智能卡的集成电路可以包括通用串行总线（USB），用于与USB主机设备通信的收发器，和连接到所述USB收发器，并且可操作在测试模式和用户模式的微处理器。 当在测试模式中，微处理器可以执行测试操作基于经由所述至少一个USB收发器从USB主机设备接收至少一个测试供应商特定请求（VSR）。 通过示例的方式，测试手术可以包括扫描从测试微处理器的控制逻辑，检测至少一个缓冲器的状态和通信状态到USB主机设备，测试数据写入到至少一个指定的缓冲器和发送测试数据 所述至少一个指定的缓冲器向USB主机设备，和/或以降低的功率工作。

公开(公告)号：EP1777535A2

公开(公告)日：2007-04-25

申请号：EP06255109.8

申请日：2006-10-03

Applicant: STMicroelectronics, Inc.

Inventor： Fruhauf, Serge F. ,  Pomet, Alain C.

IPC: G01R31/317 ,  G06K19/073

CPC classification number: G01R31/31719 ,  G06K19/07309

Abstract: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

Abstract translation: 一种装置包括由能够执行一个或多个功能的逻辑形成的多个宏小区（402-406）。 该装置还包括能够接收时钟信号并且向每个宏小区提供时钟信号的至少一个副本的时钟树（408）。 时钟树包括每个宏小区内的本地分支（410-414），其中每个本地分支能够提供时钟信号的至少一个副本。 此外，该装置包括至少一个毛刺检测电路，能够检测（418）由宏单元中的本地分支提供的时钟信号的一个或多个副本中的毛刺。

公开(公告)号：EP1772811A2

公开(公告)日：2007-04-11

申请号：EP06255105.6

申请日：2006-10-03

Applicant: STMicroelectronics, Inc.

Inventor： Fruhauf, Serge F. ,  Pomet, Alain C.

IPC: G06F21/02 ,  G06F21/00

CPC classification number: H04L9/003 ,  G06F21/755 ,  G06F21/77 ,  G06F2221/2123 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.

Abstract translation: 一种安全装置，包括能够存储信息的存储器。 因此，该安全装置包括：能够确保在存储器中的信息的安全微控制器。 安全微控制器包括寄存器的复数。 因此，安全微控制器包括能够接收由所述寄存器中的至少一个中提供至少一个输出值的组合逻辑。 组合逻辑因此能够使用所述至少一个接收到的输出值执行一个或多个的组合操作。 此外，安全微控制器包括能够使一个或多个寄存器和组合逻辑改变状态，并在一个或多个假周期消耗的电流的空周期的电路。