公开(公告)号：EP1271548A1

公开(公告)日：2003-01-02

申请号：EP01305439.0

申请日：2001-06-22

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: An associative memory comprises an array of memory cells arranged in rows and columns, each row comprising a plurality of segments each of which comprises a set of said memory cells, wherein each memory cell has compare circuitry for comparing input data with data stored therein and for generating a cell match signal when said input data matches said stored data and match signal combining circuitry for receiving a match signal from a preceding cell in the set and operable to generate a logical value dependent on the match signal of the current cell and the match signal of the preceding cell whereby each segment generates a resultant segment logical value, the memory further comprising combinatorial logic circuitry associated with each row for combining said resultant segment logical values to generate a final output match signal for that row.

Abstract translation: 相关存储器包括以行和列排列的存储器单元的阵列，每行包括多个段，每个段包括一组所述存储单元，其中每个存储单元具有用于将输入数据与存储在其中的数据进行比较的比较电路， 当所述输入数据与所述存储的数据匹配并且匹配信号组合电路用于从所述组中的先前小区接收匹配信号并且可操作以产生取决于当前小区的匹配信号和匹配信号的逻辑值时，产生小区匹配信号 其中每个段产生合成段逻辑值，所述存储器还包括与每行相关联的组合逻辑电路，用于组合所述合成段逻辑值以产生该行的最终输出匹配信号。

公开(公告)号：EP1197969A1

公开(公告)日：2002-04-17

申请号：EP01307194.9

申请日：2001-08-23

Applicant: STMicroelectronics, Ltd.

Inventor： Hammond, Paul ,  Barnes, William

IPC: G11C29/00

CPC classification number: G11C29/32

Abstract: The present invention proposes a method of disabling a particular decoder output during scan-mode testing without impacting the critical path during either scan-mode or the normal mode of operation. During scan-mode testing a known bit stream may be programmed into latches and provides a means of functional testing the device in question. Three embodiments are used in conjunction with a disable driver to pull an intermediate node HIGH. The intermediate node is inverted by an output driver, which disables the relevant decoder output. The first embodiment involves using a full CMOS gate, the second embodiment uses ratio logic and the third uses a weak pull-up resistor.

Abstract translation: 本发明提出了一种在扫描模式测试期间禁用特定解码器输出的方法，而不影响在扫描模式或正常操作模式期间的关键路径。 在扫描模式测试期间，已知比特流可以被编程到锁存器中，并提供对所讨论的设备进行功能测试的手段。 三个实施例与禁用驱动器结合使用以将中间节点拉高。 中间节点由输出驱动器反相，禁用相关的解码器输出。 第一实施例涉及使用全CMOS栅极，第二实施例使用比率逻辑，第三实施例使用弱上拉电阻。

公开(公告)号：EP1026826A3

公开(公告)日：2000-08-30

申请号：EP99310180.7

申请日：1999-12-17

Applicant: Stmicroelectronics, Ltd.

Inventor： Barnes, William

IPC: H03K5/24

CPC classification number: H03K5/249 ,  H03K3/356139 ,  H03K5/2481

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

公开(公告)号：EP1026826A2

公开(公告)日：2000-08-09

申请号：EP99310180.7

申请日：1999-12-17

Applicant: Stmicroelectronics, Ltd.

Inventor： Barnes, William

IPC: H03K5/24

CPC classification number: H03K5/249 ,  H03K3/356139 ,  H03K5/2481

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract translation: 具有用于比较第一和第二电压的比较装置的比较器电路具有用于向所述比较装置提供电流的电流源电路，所述电流源电路具有用于接收具有第一和第二状态的时钟信号的输入，由此比较装置开始比较 当时钟信号从第一状态转换到第二状态时的第一和第二电压; 以及用于确定何时所述比较装置已经完成所述第一和第二电压的比较以及用于在所述比较已经完成时关断所述电流源电路并因此断开所述比较装置的装置。