公开(公告)号：EP1197969A1

公开(公告)日：2002-04-17

申请号：EP01307194.9

申请日：2001-08-23

Applicant: STMicroelectronics, Ltd.

Inventor： Hammond, Paul ,  Barnes, William

IPC: G11C29/00

CPC classification number: G11C29/32

Abstract: The present invention proposes a method of disabling a particular decoder output during scan-mode testing without impacting the critical path during either scan-mode or the normal mode of operation. During scan-mode testing a known bit stream may be programmed into latches and provides a means of functional testing the device in question. Three embodiments are used in conjunction with a disable driver to pull an intermediate node HIGH. The intermediate node is inverted by an output driver, which disables the relevant decoder output. The first embodiment involves using a full CMOS gate, the second embodiment uses ratio logic and the third uses a weak pull-up resistor.

Abstract translation: 本发明提出了一种在扫描模式测试期间禁用特定解码器输出的方法，而不影响在扫描模式或正常操作模式期间的关键路径。 在扫描模式测试期间，已知比特流可以被编程到锁存器中，并提供对所讨论的设备进行功能测试的手段。 三个实施例与禁用驱动器结合使用以将中间节点拉高。 中间节点由输出驱动器反相，禁用相关的解码器输出。 第一实施例涉及使用全CMOS栅极，第二实施例使用比率逻辑，第三实施例使用弱上拉电阻。