公开(公告)号：EP1286358A1

公开(公告)日：2003-02-26

申请号：EP01305427.5

申请日：2001-06-22

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan ,  Beat, Robert

IPC: G11C29/00

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C29/50

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for coupling the second node to a respective second bit-line; and a respective individual gate arrangement having an output, and inputs connected to the respective first and second bit-lines, and being arranged to provide an output of a first type when the respective first and second bit lines are both within a low potential range, and otherwise provide an output of a second type; and the apparatus comprising a common gate arrangement having an output, and inputs connected to the outputs of the individual gate arrangements, the common gate arrangement being arranged to provide an output of a first type when the inputs are all of the same type, and otherwise provide an output of a second type.

Abstract translation: 用于测试集成电路的设备，所述集成电路包括通过公共字线连接的多个半导体存储器单元，每个存储器单元包括：交叉耦合排列的相应第一和第二晶体管以形成双稳态锁存器， 第一晶体管代表用于存储高电位或低电位状态的相应第一节点，并连接到相应的第一半导体装置，用于替换从第一节点泄漏的电荷并连接到相应的第一开关装置，可由公共字线激活， 用于将相应的第一节点耦合到相应的第一位线，第二晶体管的漏极表示相应的第二节点，用于存储高电位或低电位状态并连接到相应的第二半导体装置，用于替换从相应的第二位线泄漏的电荷 节点并连接到相应的第二交换装置，可由com激活 单字线，用于将第二节点耦合到相应的第二位线; 以及各自的具有输出端的单独的栅极布置，以及连接到相应的第一和第二位线的输入端，并且当相应的第一和第二位线都处于低电位范围内时，布置成提供第一类型的输出， 否则提供第二类型的输出; 并且该设备包括具有输出的共栅极布置和连接到各个栅极布置的输出的输入端，共同的栅极布置被设置为当输入都是相同类型时提供第一类型的输出，否则 提供第二种输出。

公开(公告)号：EP1079526A1

公开(公告)日：2001-02-28

申请号：EP00303979.9

申请日：2000-05-11

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan

IPC: H03K19/0948 ,  H03K19/017

CPC classification number: H03K19/01707 ,  H03K19/0948

Abstract: A ratio logic gate has a current mirror (20) controlled by the pull-down transistors (10-13) and supplying a half size pull-down transistor (23). When one or more of the input pull-down transistors (10-13) is on, the mirror current overcomes the output pull-down transistor (23) to provide a high potential output. Process tolerances between p and n type devices is thus avoided.

Abstract translation: 比率逻辑门具有由下拉晶体管（10-13）控制并提供半尺寸下拉晶体管（23）的电流镜（20）。 当一个或多个输入下拉晶体管（10-13）导通时，镜电流克服输出下拉晶体管（23）以提供高电位输出。 因此避免了p型和n型器件之间的工艺公差。

公开(公告)号：EP0953891A1

公开(公告)日：1999-11-03

申请号：EP99300599.0

申请日：1999-01-27

Applicant: Stmicroelectronics, Ltd.

Inventor： Barnes, William Bryan

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A current mirror has an input node for receiving an input current and an output node for filing an output current. First, second and third transistors are provided with each transistor having first and second current path terminals and a control terminal. The control terminals of the first and second transistors are connected to each other. The first current path terminal of the first transistor and one of the current path terminals of the second transistor are connected to a power supply. The control terminal of the third transistor is connected to the input node. One of the first and second current path terminals of the third transistor are connected to the output node and the other of the first and second current path terminals of the third transistor are connected to the other of the first and second current path terminals of the second transistor. A resistive element is arranged between the input node and the second current path terminal of the first transistor. The control terminals of the first and second transistors are connected to a node between the resistive element and a second current path terminal of the first transistor. The resistive element is a transistor of the opposite plurality to the first, second and third transistors.

Abstract translation: 电流镜具有用于接收输入电流的输入节点和用于归档输出电流的输出节点。 首先，提供具有第一和第二电流路径端子和控制端子的每个晶体管的第二和第三晶体管。 第一和第二晶体管的控制端子彼此连接。 第一晶体管的第一电流通路端子和第二晶体管的电流通路端子之一连接到电源。 第三晶体管的控制端连接到输入节点。 第三晶体管的第一和第二电流通路端子之一连接到输出节点，第三晶体管的第一和第二电流通路端子中的另一个连接到第二晶体管的第一和第二电流通路端子中的另一个 晶体管。 电阻元件布置在第一晶体管的输入节点和第二电流路径端子之间。 第一和第二晶体管的控制端子连接到第一晶体管的电阻元件和第二电流通路端子之间的节点。 电阻元件是与第一，第二和第三晶体管相反的多个晶体管。

公开(公告)号：EP1098438A1

公开(公告)日：2001-05-09

申请号：EP00309651.8

申请日：2000-11-01

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/356113 ,  H03K3/012

Abstract: A complementary logic circuit is provided which provides improved switching times over known complementary logic circuits. The circuit includes a further n-type transistor connected in series between a p-type and an n-type transistor. This additional n-type transistor has its gate permanently connected to an upper supply voltage, Vdd. When switching occurs the n-type transistor is effectively open circuit. This allows the first n-type transistor to switch on by a substantial amount quite quickly without 'fighting' the presently conducting p-type transistor. When the first n-type transistor has been turned substantially on does the second transistor becomes conductive. Then the p-type transistor is substantially turned off and no longer opposes the turning on of the first n-type transistor.

Abstract translation: 提供了一种互补逻辑电路，其提供了比已知的互补逻辑电路更好的切换时间。 该电路包括在p型和n型晶体管之间串联连接的另一n型晶体管。 该附加的n型晶体管的栅极永久地连接到上电源电压Vdd。 当切换发生时，n型晶体管有效开路。 这允许第一n型晶体管相当快地接通大量，而不会使当前导电的p型晶体管“战斗”。 当第一n型晶体管已基本上导通时，第二晶体管导通。 然后，p型晶体管基本截止，并且不再与第一n型晶体管的导通相对。