公开(公告)号：EP1286358A1

公开(公告)日：2003-02-26

申请号：EP01305427.5

申请日：2001-06-22

Applicant: STMicroelectronics, Ltd.

Inventor： Barnes, William Bryan ,  Beat, Robert

IPC: G11C29/00

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C29/50

Abstract: Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each memory cell comprising: respective first and second transistors in cross-coupled arrangement to form a bistable latch, the drain of the first transistor representing a respective first node for storing a high or low potential state and being connected to a respective first semiconductor arrangement for replacing charge leaked from the first node and being connected to a respective first switching means, activatable by the common word-line, for coupling the respective first node to a respective first bit-line, the drain of the second transistor representing a respective second node for storing a high or low potential state and being connected to a respective second semiconductor arrangement for replacing charge leaked from the respective second node and being connected to a respective second switching means, activatable by the common word line, for coupling the second node to a respective second bit-line; and a respective individual gate arrangement having an output, and inputs connected to the respective first and second bit-lines, and being arranged to provide an output of a first type when the respective first and second bit lines are both within a low potential range, and otherwise provide an output of a second type; and the apparatus comprising a common gate arrangement having an output, and inputs connected to the outputs of the individual gate arrangements, the common gate arrangement being arranged to provide an output of a first type when the inputs are all of the same type, and otherwise provide an output of a second type.

Abstract translation: 用于测试集成电路的设备，所述集成电路包括通过公共字线连接的多个半导体存储器单元，每个存储器单元包括：交叉耦合排列的相应第一和第二晶体管以形成双稳态锁存器， 第一晶体管代表用于存储高电位或低电位状态的相应第一节点，并连接到相应的第一半导体装置，用于替换从第一节点泄漏的电荷并连接到相应的第一开关装置，可由公共字线激活， 用于将相应的第一节点耦合到相应的第一位线，第二晶体管的漏极表示相应的第二节点，用于存储高电位或低电位状态并连接到相应的第二半导体装置，用于替换从相应的第二位线泄漏的电荷 节点并连接到相应的第二交换装置，可由com激活 单字线，用于将第二节点耦合到相应的第二位线; 以及各自的具有输出端的单独的栅极布置，以及连接到相应的第一和第二位线的输入端，并且当相应的第一和第二位线都处于低电位范围内时，布置成提供第一类型的输出， 否则提供第二类型的输出; 并且该设备包括具有输出的共栅极布置和连接到各个栅极布置的输出的输入端，共同的栅极布置被设置为当输入都是相同类型时提供第一类型的输出，否则 提供第二种输出。