公开(公告)号：EP1439398A1

公开(公告)日：2004-07-21

申请号：EP03250275.9

申请日：2003-01-16

Applicant: STMicroelectronics, Ltd.

Inventor： Ravenhill, Paul ,  Dellow, Andrew ,  Hutson, Matthew

IPC: G01R31/3185

CPC classification number: G01R31/318558 ,  G01R31/31719 ,  G01R31/318536

Abstract: A semiconductor integrated circuit has logic components for testing using scan chains. Scan chains comprise latch components. The scan chains are arranged such that any latch components for storing secret data, such as passwords or keys, are arranged in separate secure scan chains separate from the main scan chains. A security arrangement prevents access to this secure scan chains to unauthorised parties.

Abstract translation: 半导体集成电路具有用于使用扫描链进行测试的逻辑组件。 扫描链包括闩锁部件。 扫描链被布置成使得用于存储秘密数据（例如密码或密钥）的任何锁存部件被布置在与主扫描链分开的分开的安全扫描链中。 一种安全措施防止访问这个安全的扫描链到未经授权的方面。

公开(公告)号：EP1244214A1

公开(公告)日：2002-09-25

申请号：EP01302735.4

申请日：2001-03-23

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew

IPC: H03K23/68 ,  H03K23/54

CPC classification number: H03K23/68 ,  H03K23/546

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes is achieved by a multiplexer selecting one of two signals every half cycle.

Abstract translation: 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。

公开(公告)号：EP1768408A1

公开(公告)日：2007-03-28

申请号：EP05254789.0

申请日：2005-07-29

Applicant: STMicroelectronics Ltd.

Inventor： Dellow, Andrew ,  Bennett, Peter

IPC: H04N7/167 ,  H04L9/00

CPC classification number: H04N7/1675 ,  H04L9/0891 ,  H04L9/3247 ,  H04L2209/56 ,  H04L2209/601 ,  H04N21/4181 ,  H04N21/43607 ,  H04N21/4405 ,  H04N21/8166

Abstract: A method, apparatus and system for restricting the use of a data item (PBK1) stored within a circuit (3), the method comprising the steps of:
- receiving and storing the data item in the circuit (3);
- receiving a signature (201), the signature (201) being derived from data in a data item field (hash of PBK1=H(PBK1)-207) and data in one or more value fields (VCC 203, STC 205), the signature (201) being in a (RSA) coded form generated according to a predetermined algorithm (RSA):
- decoding the signature (201) and extracting information representative of the data H(PBJ1) in the data item field (207) and information representative of the values VCC & STC in the one or more value fields (203, 205);
- determining whether the information representative of the data extracted from the data item field (207) of the signature (201) corresponds to a predetermined value stored in the circuit (3) and whether the information representative of each value extracted from each value field (203,205) of the signature (201) corresponds to a corresponding further predetermined value stored in the circuit (3); and
- generating a comparison signal according to the result of the determinations;
in which use of the data item (PBK1) is restricted according to the state of the comparison signal.

Abstract translation: 对于限制使用的数据项的方法，设备和系统（PBK1）存储在电路（3）内，该方法包括以下步骤： - 接收和在电路（3）存储数据项; - 接收的签名（201），签名（201）被从数据导出的数据项字段（散列PBK1 = H（PBK1）-207），并且在一个或多个值字段中的数据（VCC 203，STC 205） 在（RSA）编码的形式是所述签名（201）生成的雅丁预定算法（RSA）： - 解码签名（201），并提取代表该数据项字段（207）中的数据H（pBJ1）的信息和 代表值VCC＆STC在所述一个或多个值的字段（203，205）的信息; - 确定性采矿是否代表从签名（201）的数据项字段（207）中提取的数据的信息对应于存储在电路中的预定值（3），以及是否代表从每个值字段提取的每个值的信息（ 签名（201）的203.205）对应于存储在电路（3）的相应的另外的预定值; 以及 - 产生一个比较信号gemäß到的确定的结果; 在其中使用的数据项（PBK1）的被限制gemäß于比较信号的状态。

公开(公告)号：EP1333380A1

公开(公告)日：2003-08-06

申请号：EP02250645.5

申请日：2002-01-30

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit (210) for use in direct memory access (DMA) has 3 sources (214,215,216) which communicate with a bus (230) through a bus interface (220). A DMA access signal generator (290) is coupled to the bus interface (220) and asserts a DMA access output signal at DMA access signal pins (296,396) whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the 3 sources is thereby avoided. With targets on two separate integrated circuits (212,312), a single DMA access pin (396) can be used for the two targets (248,349), chip select signal at chip select pins (506,516) on the source integrated cicuit (210) indicate which of the two targets the DMA access is intended for.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路（210）具有通过总线接口（220）与总线（230）通信的3个源（214,215,216）。 DMA访问信号发生器（290）耦合到总线接口（220），并且每当任何一个源需要DMA访问时，就在DMA访问信号引脚（296,396）断言DMA访问输出信号。 因此避免了对于3个源中的每一个的单独的DMA访问信号引脚的需要。 在两个独立集成电路（212,312）上的目标器件中，可以为两个目标（248,349）使用单个DMA访问引脚（396），源集成电路（210）上芯片选择引脚（506,516）处的芯片选择信号指示哪个 的DMA访问旨在的两个目标。

公开(公告)号：EP1241788A1

公开(公告)日：2002-09-18

申请号：EP01302299.1

申请日：2001-03-13

Applicant: STMicroelectronics, Ltd.

Inventor： Dellow, Andrew

IPC: H03K23/66 ,  H03K23/68 ,  H03K21/10

CPC classification number: H03K23/68 ,  H03K21/10 ,  H03K23/66

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs (A,B) adjacent such that one output is equal to the other delayed by one clock period. The outputs (A,B) are passed to a multiplexer (6) via further logic, the multiplexer selecting one of two inputs (X,Y) depending on whether a clock is high or low. Program logic (40) is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively "deleting" the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an "even" mark space ratio.

Abstract translation: 数字分频器具有单个循环移位器寄存器，其加载可变长度的位序列并且具有相邻的两个输出（A，B），使得一个输出等于延迟一个时钟周期的另一个输出。 输出（A，B）经由另外的逻辑被传送到多路复用器（6），多路器根据时钟是高还是低选择两个输入（X，Y）中的一个。 提供程序逻辑（40），使得通过检测0和1之间的位序列的变化，并且当检测到改变时选择性地“删除”前半个时钟周期，电路可配置为奇数，偶数或者半整数除法。 这允许偶数，奇数或半整数时钟分频与“偶数”标记空间比。