公开(公告)号：EP1439398A1

公开(公告)日：2004-07-21

申请号：EP03250275.9

申请日：2003-01-16

Applicant: STMicroelectronics, Ltd.

Inventor： Ravenhill, Paul ,  Dellow, Andrew ,  Hutson, Matthew

IPC: G01R31/3185

CPC classification number: G01R31/318558 ,  G01R31/31719 ,  G01R31/318536

Abstract: A semiconductor integrated circuit has logic components for testing using scan chains. Scan chains comprise latch components. The scan chains are arranged such that any latch components for storing secret data, such as passwords or keys, are arranged in separate secure scan chains separate from the main scan chains. A security arrangement prevents access to this secure scan chains to unauthorised parties.

Abstract translation: 半导体集成电路具有用于使用扫描链进行测试的逻辑组件。 扫描链包括闩锁部件。 扫描链被布置成使得用于存储秘密数据（例如密码或密钥）的任何锁存部件被布置在与主扫描链分开的分开的安全扫描链中。 一种安全措施防止访问这个安全的扫描链到未经授权的方面。