公开(公告)号：EP2202633A1

公开(公告)日：2010-06-30

申请号：EP09180312.2

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Sun, Hong- Xia ,  Wang, Kai- Feng ,  Zhu, Peng- Fei ,  Wu, Yong- Qiang

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/384

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract translation: 一种用于恢复架构寄存器映射表（ARMT）的系统。 该系统包括第一数量的采集电路和解码电路，第二数量的选择电路和使能电路。 与每个物理寄存器和适当架构寄存器之间的映射相关的信息在仅第四个指令周期中的一个中仅由一个且仅一个采集电路从物理寄存器映射表（PRMT）获得。 每个解码电路的输入端耦合到一个不同的采集电路的输出端，并且能够在其输出端将其输入转换为第三个位宽的二进制串选择码。 每个选择电路被配置为从与该选择电路相关联的位位置从每个选择代码接收一位。 使能电路被配置为适当地启用从PRMT到ARMT的信息的映射。