公开(公告)号：EP4102335A1

公开(公告)日：2022-12-14

申请号：EP22305741.5

申请日：2022-05-19

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  TUDOSE, Andrei ,  CLERICI, Francesco ,  BUTTA', Pasquale

IPC: G05F1/46 ,  G06F1/26

Abstract: A circuit (10), such as a microcontroller unit, MCU for instance, comprises a first node (VBAT) configured to be brought to a first voltage such as the supply voltage from a battery (LB), a second node (VDDIO) configured to be coupled (180) with an electrically powered device (ED) such as an external memory to provide electrical supply power thereto, and a voltage regulator (100) such as a LDO regulator embedded in the circuit (10) intermediate the first node (VBAT) and the second node (VDDIO). The voltage regulator (100) is activatable in a first, startup mode during which the voltage regulator (100) applies to the second node (VDDIO), and thus to the external device (ED), a voltage increasing towards a supply threshold (160). The circuit (10) comprises control circuitry (20) activatable (16, 160, vdig_en, 22) in response to the voltage at the second node (VDDIO) reaching the supply threshold (160) to bring the voltage regulator (100) to a second mode of operation (1008) wherein a programmable regulated voltage higher than the supply threshold is applied to the second node (VDDIO). The circuit (100) is configured (162) to receive low-power operation requests (1010) and, in response to low-power operation requests (1010) received, to deactivate a first high-drive regulator circuitry (102) in the voltage regulator (100) and activate a second low-power regulator circuitry (104) thus providing a third, low-power mode of operation of the circuit (10).

公开(公告)号：EP3702886A1

公开(公告)日：2020-09-02

申请号：EP20157715.2

申请日：2020-02-17

Applicant: STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  BUTTA', Pasquale

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  H02M1/00

Abstract: A method for managing the power supply in an electronic circuit comprising a processing system (11; 11'), in particular a general purpose microcontroller or a System-on-Chip or a subsystem thereof, with a radio-frequency embedded circuit (12),
said processing system (11; 11') comprising
at least a processing core (30, V12I, VI2O) and a first power regulation module (111') supplying a first regulated voltage (V12) to said processing core (30),
said radio frequency embedded circuit (12) comprising a second power regulation module (121) supplying a second regulated voltage (V reg ) to circuits (122) of the radio-frequency embedded circuit including a radio frequency transceiving portion (124), said second power regulation module (122) comprising a switched-mode power supply (1211) and generating a second regulated voltage (V reg ),
said method comprising coupling said second regulated voltage (V reg ) as voltage input of said first power regulation module (1111), said first power regulation module (1111) which generates as an output a respective first regulated voltage (V regm ) for said processing core (30),
controlling said second power regulation module (121) to operate according to a plurality of operation modes (LP1, LP2, A1, A2, LP3, LP4) including
one or more sleep modes (LP1, LP2) in which both the DC-DC converter (1211) and the second linear regulator (121) are off and
one or more active modes (A1, A2) in which both the DC-DC converter (1211) and the second linear regulator (121) are on,
wherein said second power regulation module (122) comprises a second linear regulator (1212) and
said plurality of modes (LP1, LP2, A1, A2, LP3, LP4) includes
a first further sleep mode (LP3) in which the switched-mode power supply (1211) is off and the second linear regulator (1212) is on and
a second further sleep mode in which the switched-mode power supply (1211) is on and the second linear regulator (1212) is off.