公开(公告)号：EP3885924A1

公开(公告)日：2021-09-29

申请号：EP21162262.6

申请日：2021-03-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： NANDLINGER, Mr. Rolf ,  OLEXA, Mr. Radek

IPC: G06F13/40

Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

公开(公告)号：EP3736657A1

公开(公告)日：2020-11-11

申请号：EP20171289.0

申请日：2020-04-24

Applicant: STMicroelectronics Application GmbH

Inventor： NANDLINGER, Mr. Rolf

IPC: G06F1/04 ,  H04L12/40

Abstract: A processing system is described. The processing system comprises a digital processing unit (102) programmable as a function of a firmware stored to a non-volatile memory and a resource (ADC, IF1, IF2) connected to the digital processing unit (102) via a communication system (108).
The processing system comprises also a time reference circuit (122) comprising a first digital counter circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count, and a time base distribution circuit configured to generate a time base signal ( TBI0..TBIn ) by selecting a subset of the bits of the system time signal, wherein the time base signal ( TBI0..TBIn ) is provided to the resource (ADC, IF1, IF2).
Specifically, the resource (ADC, IF1, IF2) is configured to detect a given event, store the time base signal ( TBI0 .. TBIn ) to a register (REG1..REG3) in response to the event, and signal the event to the digital processing unit (102). Conversely, the digital processing unit (102) is adapted to, in response to the event having been signaled by the resource (ADC, IF1, IF2), read via the communication system (108) the time base signal ( TBI0 .. TBIn ) from the register (REG1..REG3).