公开(公告)号：EP4152171A1

公开(公告)日：2023-03-22

申请号：EP22206499.0

申请日：2021-03-12

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

Inventor： NANDLINGER, Rolf ,  OLEXA, Radek

IPC: G06F13/40

Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

公开(公告)号：EP4012984A1

公开(公告)日：2022-06-15

申请号：EP21212062.0

申请日：2021-12-02

Applicant: STMicroelectronics Application GmbH

Inventor： RENNIG, Fred ,  NANDLINGER, Rolf

IPC: H04L12/40

Abstract: A processing system is described. The processing system comprises a first CAN XL communication system (50 1 ) and a second CAN XL communication system (50 2 ), wherein each CAN XL communication system (50 1 , 50 2 ) comprises a CAN XL protocol controller configured to generate a NRZ encoded transmission signal (TXD) and receive a NRZ encoded reception signal (RXD). Each CAN XL communication system (50 1 , 50 2 ) is configured to generate a first transmission signal (TXD1) by selecting the NRZ encoded transmission signal (TXD) or a PWM signal generated as a function of the NRZ encoded transmission signal (TXD).
Specifically, the processing system (10a) comprises a bus (22) having a transmission node (TX2) and a reception node (RX2), wherein the bus (22) is configured to receive from each CAN XL communication system (50 1 , 50 2 ) a respective second transmission signal (TXD2) and drive the logic level at the transmission node (TX2) as a function of the logic levels of the second transmission signals (TXD2), and provide to each CAN XL communication system (50 1 , 50 2 ) a respective second reception signal (RXD2) having a logic level determined as a function of the logic level at the reception node (RX2). Moreover, the processing system comprises a switching circuit (24, 224, 306, 308, 52, 520) configured to support a plurality of modes, wherein, in a first mode, the switching circuit (24, 224, 306, 308, 52, 520) is configured to provide the NRZ encoded transmission signals (TXD) of the CAN XL communication systems (50 1 , 50 2 ) as the second transmission signals (TXD2) to the bus system (22), and provide the respective second reception signal (RXD2) received from the bus (22) to the CAN XL protocol controllers (300) of the CAN XL communication system (50 1 , 50 2 ).

公开(公告)号：EP4095704A1

公开(公告)日：2022-11-30

申请号：EP22174093.9

申请日：2022-05-18

Applicant: STMicroelectronics Application GmbH

Inventor： NANDLINGER, Rolf ,  COLOMBO, Roberto

IPC: G06F13/28

Abstract: A processing system (10a) is described. The processing system (10a) comprises a microprocessor (1020) programmable via software instructions, a memory controller (100) configured to be connected to a memory (104, 104b), a communication system (114) connecting the microprocessors (1020) to the memory controller (100), a cryptographic co-processor (40a) and a Serial Inter-Processor Interface, SIPI, communication interface (50a). The processign system (10a) also comprises a first (DMA T1 ) and a second configurable DMA channel (DMA T2 ).
Specifically, in a first configuration, the first DMA channel (DMA T1 ) is configured to transfer data from the memory (104b) to the cryptographic co-processor (40a), and the second DMA channel (DMA T2 ) is configured to transfer the encrypted data via two loops from the cryptographic co-processor (40a) to the SIPI communication interface (50a).
Conversely, in a second configuration, the second DMA channel (DMA T2 ) is configured to transfer received data via two loops from the SIPI communication interface (50a) to the cryptographic co-processor (40a), and the first DMA channel (DMA T1 ) is configured to transfer the decrypted data from the cryptographic co-processor (40a) to a memory (104b).

公开(公告)号：EP3761183A1

公开(公告)日：2021-01-06

申请号：EP20183631.9

申请日：2020-07-02

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： TRIVEDI, Nirav Prashantkumar ,  ATAL, Sandip ,  NANDLINGER, Rolf

IPC: G06F13/28 ,  H03M1/12 ,  H03M1/38

Abstract: An analog-to-digital conversion system (500) is described. The analog-to-digital conversion system (500) comprises an analog-to-digital converter (100), a multiplexer (200), wherein the multiplexer has a plurality of input channels that are configured to be coupled to a plurality of analog input signals (201), and wherein an output terminal of the multiplexer (203) is coupled to an input terminal of the ADC (102). The analog-to-digital conversion system (500) comprises also a digital interface circuit (300) configured to be coupled between the ADC (100) and a processor (400). The digital interface circuit (300) is configured to receive a sequence of commands (CMD0 FRM..CMD3 FRM) from the processor (400), wherein each command of the sequence of commands (CMD0 FRM..CMD3 FRM) comprises a channel number (ADC CH NUM) that indicates an input channel (201) of the multiplexer (200), wherein channel numbers contained in the sequence of commands define a channel sequence. The digital interface circuit (300) stores the sequence of commands (CMD0 FRM..CMD3 FRM) in a command First-In First-Out, FIFO, buffer (305) of the digital interface circuit (300) and sends the sequence of commands (CMD0 FRM..CMD3 FRM) stored in the command FIFO buffer (305) to the ADC (100) for a first time to control operation of the ADC, wherein analog input signals at input channels of the multiplexer (200) specified by the channel sequence are converted into digital data sequentially for the first time. Moreover, the digital interface circuit (300) sends the same sequence of commands (CMD0 FRM..CMD3 FRM) stored in the command FIFO buffer (305) to the ADC (100) for a second time, wherein the analog input signals at the input channels of the multiplexer (200) specified by the channel sequence are converted into digital data sequentially for the second time.