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    ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING
    1.
    发明申请
    ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING 审中-公开
    使用片上时钟的ATPG设计失败的飞行测试和调试逻辑

    公开(公告)号：US20170023647A1

    公开(公告)日：2017-01-26

    申请号：US15284070

    申请日：2016-10-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

    Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

    Abstract translation: 本文公开的系统包括片上时钟控制器（OCC）电路，其接收测试模式并响应于测试模式响应地产生输出时钟脉冲。 OCC测试电路耦合到OCC电路，并被配置为检测对应于由OCC控制器电路产生的输出时钟脉冲的数据，并产生相应的OCC测试输出。 测试输出逻辑电路被配置为从OCC测试电路接收OCC测试输出。 调试控制器可用于配置测试输出逻辑电路以输出OCC测试输出。

    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
    2.
    发明授权
    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking 有权
    使用片上时钟设计的ATPG故障的即时测试和调试逻辑

    公开(公告)号：US09482719B2

    公开(公告)日：2016-11-01

    申请号：US14152130

    申请日：2014-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G06F11/00 ,  G01R31/317 ,  G01R31/3181

    CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

    Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

    Abstract translation: 半导体芯片包括接收ATPG测试图案并产生响应的时钟脉冲的OCC。 OCC测试电路检测OCC电路的时钟脉冲，并提供调试数据以测试输出可配置逻辑，其也接收来自测试不同DUT触发器的其他电路的结果。 削波测试电路通过向DUT I / O提供脉冲宽度敏感的触发器输出来检测来自OCC的剪辑时钟脉冲的ATPG故障。 IR跌落测试电路检测ATPG故障是否由于某些触发器中的IR降低问题。 脉冲位操作电路改变提供给OCC和OCC产生的时钟脉冲的测试模式。 连接到测试输出可配置逻辑的调试控制器在不同测试结果之间选择供应作为输出测试信号，与ATE上的预期模式数据进行比较，并用于隔离芯片上的错误。

    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
    5.
    发明授权
    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking 有权

    公开(公告)号：US10094876B2

    公开(公告)日：2018-10-09

    申请号：US15284070

    申请日：2016-10-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3181

    Abstract: A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.

    ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING
    6.
    发明申请
    ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING 有权
    使用片上时钟的ATPG设计失败的飞行测试和调试逻辑

    公开(公告)号：US20150198663A1

    公开(公告)日：2015-07-16

    申请号：US14152130

    申请日：2014-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G01R31/3177 ,  G01R31/3181

    CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

    Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

    Abstract translation: 半导体芯片包括接收ATPG测试图案并产生响应的时钟脉冲的OCC。 OCC测试电路检测OCC电路的时钟脉冲，并提供调试数据以测试输出可配置逻辑，其也接收来自测试不同DUT触发器的其他电路的结果。 削波测试电路通过向DUT I / O提供脉冲宽度敏感的触发器输出来检测来自OCC的剪辑时钟脉冲的ATPG故障。 IR跌落测试电路检测ATPG故障是否由于某些触发器中的IR降低问题。 脉冲位操作电路改变提供给OCC和OCC产生的时钟脉冲的测试模式。 连接到测试输出可配置逻辑的调试控制器在不同测试结果之间选择供应作为输出测试信号，与ATE上的预期模式数据进行比较，并用于隔离芯片上的错误。

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