公开(公告)号：EP1536647A1

公开(公告)日：2005-06-01

申请号：EP03257455.0

申请日：2003-11-26

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Bolton, Martin ,  Carrano, Michele

IPC: H04N7/26

CPC classification number: H04N7/24 ,  H04N19/42

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output said second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract translation: 一种视频解码电路，包括：第一视频数据处理器; 第二视频数据处理器; 以及连接第一视频数据处理器和第二数据处理器的连接; 其中所述第一视频数据处理器被布置为接收包括编码视频数据的第一信号，处理所述第一信号以提供第二信号并输出​​所述第二信号。 所述第一视频数据处理器被布置为依赖于所接收的第一信号的至少一部分来处理所述第一信号。 第二视频数据处理器被布置成接收第二信号的至少一部分，处理第二信号的至少一部分以提供第三信号，并输出第三信号，第二和第三信号包括解码视频图像 流。 第二视频数据处理器被配置为根据第二信号的至少一部分的至少一部分来处理第二信号的至少一部分。

公开(公告)号：EP2309759A1

公开(公告)日：2011-04-13

申请号：EP10183232.7

申请日：2002-03-18

Applicant: STMicroelectronics Limited

Inventor： Bolton, Martin

IPC: H04N7/50 ,  H04N7/26

CPC classification number: H04N19/42 ,  H04N19/126 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61 ,  H04N19/91

Abstract: Decoding circuitry for decoding a bitstream, the circuitry including: a processor, the processor being configured to run software for: inverse quantising quantised macroblocks to generate inverse quantised macroblocks; a streaming data connection for streaming the inverse quantised macroblocks from the processor; inverse discrete cosine transform IDCT circuitry for accepting the streamed inverse quantised macroblocks and IDCT transforming them to generate reconstructed prediction error macroblocks; and an addition circuit for adding each reconstructed prediction error macroblock and its corresponding predictor macroblock, thereby to generate a respective reconstructed macroblock.

Abstract translation: 用于解码比特流的解码电路，所述电路包括：处理器，所述处理器被配置为运行软件，用于：对量化的宏块进行逆量化以产生逆量化宏块; 流式数据连接，用于从处理器流式传输逆向量化的宏块; 逆离散余弦变换IDCT电路，用于接受流式逆量化宏块和IDCT变换它们以产生重建的预测误差宏块; 以及加法电路，用于添加每个重建的预测误差宏块及其对应的预测器宏块，从而生成相应的重构宏块。