公开(公告)号：EP1536647A1

公开(公告)日：2005-06-01

申请号：EP03257455.0

申请日：2003-11-26

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.l.

Inventor： Bolton, Martin ,  Carrano, Michele

IPC: H04N7/26

CPC classification number: H04N7/24 ,  H04N19/42

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output said second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract translation: 一种视频解码电路，包括：第一视频数据处理器; 第二视频数据处理器; 以及连接第一视频数据处理器和第二数据处理器的连接; 其中所述第一视频数据处理器被布置为接收包括编码视频数据的第一信号，处理所述第一信号以提供第二信号并输出​​所述第二信号。 所述第一视频数据处理器被布置为依赖于所接收的第一信号的至少一部分来处理所述第一信号。 第二视频数据处理器被布置成接收第二信号的至少一部分，处理第二信号的至少一部分以提供第三信号，并输出第三信号，第二和第三信号包括解码视频图像 流。 第二视频数据处理器被配置为根据第二信号的至少一部分的至少一部分来处理第二信号的至少一部分。

公开(公告)号：EP1204016B1

公开(公告)日：2007-04-11

申请号：EP00830731.6

申请日：2000-11-03

Applicant: STMicroelectronics S.r.l.

Inventor： Alia, Michele ,  Carrano, Michele ,  Pistritto, Carmelo

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: Presented is a power down circuit for use in a System on Chip SOC. Within the SOC are several circuit blocks, each of them having a local clock. A system clock is coupled to the circuit blocks and is structured to act as the local clock of selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock from acting as the local clock in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shut down is received from the power control manager and after the circuit block has, in fact, shut down. Also presented is a method that can be operated using the above system. The method includes generating a system clock signal that is for use as a local clock signal for circuit blocks that have not been shutdown. A shutdown request signal is generated to selectively power down some of the circuit blocks. That shutdown request signal is transmitted to a power down circuit within the circuit block to be shutdown. Once the block to be shutdown receives the shutdown request signal, it finishes any necessary circuit operations, and then shuts down the circuit block. Once the circuit block has shut down, a shutdown acknowledgement signal is generated, and, when this signal is received at the power down circuit within the circuit block, the system clock signal is disconnected from the local clock signal.

公开(公告)号：EP1204016A1

公开(公告)日：2002-05-08

申请号：EP00830731.6

申请日：2000-11-03

Applicant: STMicroelectronics S.r.l.

Inventor： Alia, Michele ,  Carrano, Michele ,  Pistritto, Carmelo

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: Presented is a power down circuit for use in a System on Chip SOC. Within the SOC are several circuit blocks, each of them having a local clock. A system clock is coupled to the circuit blocks and is structured to act as the local clock of selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a shutdown circuit that selectively prevents the system clock from acting as the local clock in those circuit blocks that receive the shutdown signal, but the shutdown circuit only operates after both the signal to shut down is received from the power control manager and after the circuit block has, in fact, shut down. Also presented is a method that can be operated using the above system. The method includes generating a system clock signal that is for use as a local clock signal for circuit blocks that have not been shutdown. A shutdown request signal is generated to selectively power down some of the circuit blocks. That shutdown request signal is transmitted to a power down circuit within the circuit block to be shutdown. Once the block to be shutdown receives the shutdown request signal, it finishes any necessary circuit operations, and then shuts down the circuit block. Once the circuit block has shut down, a shutdown acknowledgement signal is generated, and, when this signal is received at the power down circuit within the circuit block, the system clock signal is disconnected from the local clock signal.

Abstract translation: 提供的是用于片上系统SOC的断电电路。 SOC内有几个电路模块，每个模块都有一个本地时钟。 系统时钟耦合到电路模块，并被构造成充当选定电路模块的本地时钟。 功率控制管理器提供至少部分地确定系统时钟是否将用作一些电路块的本地时钟的信号。 在电路块内有一个关闭电路，它有选择地阻止系统时钟作为接收关闭信号的那些电路块中的本地时钟，但关闭电路仅在从功率控制管理器接收到关闭信号 事实上，在电路模块关闭之后。 还介绍了一种可以使用上述系统进行操作的方法。 该方法包括生成系统时钟信号，该系统时钟信号用作尚未关闭的电路块的本地时钟信号。 产生关闭请求信号以选择性地关闭一些电路块。 该关机请求信号被传送到电路块内的关闭电路以关闭。 一旦要关闭的程序块收到关闭请求信号，它将完成所有必要的电路操作，然后关闭电路模块。 一旦电路模块关闭，将产生一个关断确认信号，并且当在电路模块内的断电电路接收到该信号时，系统时钟信号与本地时钟信号断开。