公开(公告)号：EP1304804A2

公开(公告)日：2003-04-23

申请号：EP02022060.4

申请日：2002-10-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana

IPC: H03K23/68 ,  H03K23/66

CPC classification number: H03L7/1976 ,  H03K23/68

Abstract: An improved fractional divider that provides high resolution without the need for any analog components. It comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+1' depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces said count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract translation: 改进的分数分频器，提供高分辨率，无需任何模拟组件。 它包括整数值存储装置，其包含连接到可编程计数器装置的输入的除法值“K”的整数部分，该可编程计数器装置被配置为计数值“K”或“K + 1”，这取决于一个 计数控制信号，并且产生输出信号以及终端计数信号，该终端计数信号连接到分数累加器装置的使能输入，该分数累加器装置在加法溢出时产生所述计数控制信号，并且具有连接到其结果输出的第一输入和第二输入 连接到分数值存储装置的输出，包含分频值的小数部分。

公开(公告)号：EP1416373A3

公开(公告)日：2005-01-05

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

公开(公告)号：EP1416373A2

公开(公告)日：2004-05-06

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

Abstract translation: 连接到先进先出（FIFO）存储器（301）的数据输出端的读取数据选择器（303）从奇数和偶数读指针发生器（304,305）接收选择输入。 耦合到选择器的输出端的复用器（306）选择选择器的输出作为FIFO的最终输出。 状态控制器（310）控制对最终输出的选择并输入到选择器。 还包括以下独立权利要求：（1）减少FIFO缓冲存取时间的方法; 和（2）提供FIFO缓冲器的方法。

公开(公告)号：EP1304804A3

公开(公告)日：2006-07-12

申请号：EP02022060.4

申请日：2002-10-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana

IPC: H03K23/68 ,  H03K23/66 ,  H03L7/197

CPC classification number: H03L7/1976 ,  H03K23/68

Abstract: An improved fractional divider that provides high resolution without the need for any analog components. It comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+1' depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces said count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.