公开(公告)号：EP1416373A3

公开(公告)日：2005-01-05

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

公开(公告)号：EP1416373A2

公开(公告)日：2004-05-06

申请号：EP03024591.4

申请日：2003-10-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana ,  Verma, Jayesh

IPC: G06F7/06

CPC classification number: G06F5/10

Abstract: The method and apparatus reduce access time in synchronous FIFOs with zero latency overheads. A FIFO buffer comprises FIFO means (301) storing 'n' data words, each 'm' bits wide, having an 'm' bit wide data input terminal. Furthermore, the FIFO buffer includes read data set selection means (303) connected to the data output terminals of the FIFO means and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. Odd read pointer generating means (304) provide the selection input to the data selection means (303) for selecting data at an odd read address of the read data selection means, while even read pointer generating means (305) provide the input for selecting data at an even read address. Multiplexing means (306) coupled to each of the two data output terminals of the read data set selection means select one of its outputs as the final output of the FIFO. State controlling means (310) coupled to the multiplexing means (306) control the selection of the final output and the selection input to the read data set selection means for selecting an odd read address and an even read address.

Abstract translation: 连接到先进先出（FIFO）存储器（301）的数据输出端的读取数据选择器（303）从奇数和偶数读指针发生器（304,305）接收选择输入。 耦合到选择器的输出端的复用器（306）选择选择器的输出作为FIFO的最终输出。 状态控制器（310）控制对最终输出的选择并输入到选择器。 还包括以下独立权利要求：（1）减少FIFO缓冲存取时间的方法; 和（2）提供FIFO缓冲器的方法。