公开(公告)号：EP1679797A1

公开(公告)日：2006-07-12

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361

Abstract: The invention relates to a low noise output buffer capable of operating at high speeds which allows a control of the slew rate at the raising and falling edges of an input signal (A) of the buffer. The proposed low noise output buffer (5) is inserted between first and second voltage references (VDD, GND) and comprises a main circuit (50) for which the slew rate of an input signal (A) is to be controlled, the main circuit (50) being connected to a slew rate control circuit (52), in turn inserted between the first and second voltage references (VDD, GND). Advantageously according to the invention, the slew rate control circuit (52) comprises an additional circuit (51) connected to the main circuit (50) and operating a slew rate limiting at the raising and falling edges of the input signal (A) of the low noise output buffer (5).

Abstract translation: 本发明涉及一种能够高速运行的低噪声输出缓冲器，其允许控制缓冲器的输入信号（A）的上升沿和下降沿的转换速率。 所提出的低噪声输出缓冲器（5）插入在第一和第二参考电压（VDD，GND）之间，并且包括一个主电路（50），用于输入信号（A）的转换速率被控制，主电路 （50）连接到压摆率控制电路（52），然后插入在第一和第二参考电压（VDD，GND）之间。 有利地，根据本发明，转换速率控制电路（52）包括连接到主电路（50）的附加电路（51），并且操作在输入信号（A）的上升沿和下降沿的转换速率限制 低噪声输出缓冲器（5）。

公开(公告)号：EP1679797B1

公开(公告)日：2009-09-09

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361