公开(公告)号：EP1679797A1

公开(公告)日：2006-07-12

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361

Abstract: The invention relates to a low noise output buffer capable of operating at high speeds which allows a control of the slew rate at the raising and falling edges of an input signal (A) of the buffer. The proposed low noise output buffer (5) is inserted between first and second voltage references (VDD, GND) and comprises a main circuit (50) for which the slew rate of an input signal (A) is to be controlled, the main circuit (50) being connected to a slew rate control circuit (52), in turn inserted between the first and second voltage references (VDD, GND). Advantageously according to the invention, the slew rate control circuit (52) comprises an additional circuit (51) connected to the main circuit (50) and operating a slew rate limiting at the raising and falling edges of the input signal (A) of the low noise output buffer (5).

Abstract translation: 本发明涉及一种能够高速运行的低噪声输出缓冲器，其允许控制缓冲器的输入信号（A）的上升沿和下降沿的转换速率。 所提出的低噪声输出缓冲器（5）插入在第一和第二参考电压（VDD，GND）之间，并且包括一个主电路（50），用于输入信号（A）的转换速率被控制，主电路 （50）连接到压摆率控制电路（52），然后插入在第一和第二参考电压（VDD，GND）之间。 有利地，根据本发明，转换速率控制电路（52）包括连接到主电路（50）的附加电路（51），并且操作在输入信号（A）的上升沿和下降沿的转换速率限制 低噪声输出缓冲器（5）。

公开(公告)号：EP1679797B1

公开(公告)日：2009-09-09

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361

公开(公告)号：EP1742364A3

公开(公告)日：2008-12-31

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

公开(公告)号：EP1662660A3

公开(公告)日：2007-12-12

申请号：EP05025953.0

申请日：2005-11-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Sushil Kumar ,  Garg, Paras

IPC: H03K19/003 ,  H03K3/011 ,  H03K17/14

CPC classification number: H03K3/011 ,  H03K3/3565 ,  H03K17/145 ,  H03K19/00384

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

公开(公告)号：EP1742364A2

公开(公告)日：2007-01-10

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

Abstract translation: 描述了使用亚微米CMOS技术的CMOS集成电路的改进的输入缓冲器。 亚微米CMOS技术中的器件受器件各个端口之间存在高电压的影响。 提供了一个输入电压限制电路，从而产生具有低电压容限CMOS器件的高耐压输入缓冲器。 这种改进还通过在输入缓冲级中将补偿装置添加到第一反相器级而由于制造工艺变化而降低开关级不确定性，并因此增加噪声容限。 由电路产生的滞后特性降低了制造工艺变化的影响。 该电路可以容易地连接到其他块并且与较高电压CMOS技术电路一起安全地工作，同时实现薄栅极氧化物的高速优势。 通过避免电路中的直流电流流动的任何可能性来实现低功耗。

公开(公告)号：EP1662660A2

公开(公告)日：2006-05-31

申请号：EP05025953.0

申请日：2005-11-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Sushil Kumar ,  Garg, Paras

IPC: H03K19/003

CPC classification number: H03K3/011 ,  H03K3/3565 ,  H03K17/145 ,  H03K19/00384

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Abstract translation: 在本发明的装置和方法，用于提供相对于温度，工艺和MOS电路的电源电压变化补偿已经提出。 本发明提供在过程中，温度和电压检测电路，其控制体偏置并在CMOS电路中的器件的驱动的变化。 检测电路是独立的要被控制的CMOS电路中的任何输入或内部信号。