公开(公告)号：EP1742364A3

公开(公告)日：2008-12-31

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

公开(公告)号：EP1742364A2

公开(公告)日：2007-01-10

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

Abstract translation: 描述了使用亚微米CMOS技术的CMOS集成电路的改进的输入缓冲器。 亚微米CMOS技术中的器件受器件各个端口之间存在高电压的影响。 提供了一个输入电压限制电路，从而产生具有低电压容限CMOS器件的高耐压输入缓冲器。 这种改进还通过在输入缓冲级中将补偿装置添加到第一反相器级而由于制造工艺变化而降低开关级不确定性，并因此增加噪声容限。 由电路产生的滞后特性降低了制造工艺变化的影响。 该电路可以容易地连接到其他块并且与较高电压CMOS技术电路一起安全地工作，同时实现薄栅极氧化物的高速优势。 通过避免电路中的直流电流流动的任何可能性来实现低功耗。