公开(公告)号：EP1447752A2

公开(公告)日：2004-08-18

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.

Abstract translation: 本发明提供一个可扩展的方法，用于在多处理器体系结构实现FFT / IFFT计算确实由第一“日志2 P”阶段的计算后消除了对处理器间通信的需要提供改进的吞吐量在实施使用“P”的处理元件 ，包括同时计算在任一单个处理器或每个“P”处理器的第一“日志2 P”阶段，每个阶段蝴蝶和分发寻求做各链中的“P”的处理器之间的所有后续阶段中的蝴蝶的计算 的级联蝴蝶由...组成这些蝴蝶thathave连接在一起的输入和输出，通过相同的处理器处理。 因此本发明提供一种系统，用于在多处理器体系结构获得可扩展的实施FFT / IFFT计算的那样通过在实施使用“P”消除了对处理器间通信的需要的第一个“登录2 P”阶段的计算后提供改进的吞吐量 处理元件。

公开(公告)号：EP1447752A3

公开(公告)日：2006-02-22

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.