公开(公告)号：EP1585024B1

公开(公告)日：2007-10-10

申请号：EP05102697.9

申请日：2005-04-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G06F5/06 ,  G11C7/10

CPC classification number: G06F5/10 ,  G11C7/1006

公开(公告)号：EP1585024A1

公开(公告)日：2005-10-12

申请号：EP05102697.9

申请日：2005-04-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G06F5/06 ,  G11C7/10

CPC classification number: G06F5/10 ,  G11C7/1006

Abstract: An improved on-chip storage memory for storing variable data bits comprising an on-chip storage memory system for storing variable data bits comprising a memory for storing data bits; a wrapper for converting said memory into a first-in first-out (FIFO) memory; and a controller for performing operations on said memory.

Abstract translation: 一种用于存储可变数据位的改进的片上存储存储器，包括片上存储存储器系统，用于存储包括用于存储数据位的存储器的可变数据位; 用于将所述存储器转换成先进先出（FIFO）存储器的包装器; 以及用于对所述存储器执行操作的控制器。

公开(公告)号：EP1672791A3

公开(公告)日：2008-09-17

申请号：EP05112285.1

申请日：2005-12-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Tiwari, Naveen ,  Singh, Balwant

IPC: H03K3/03

CPC classification number: G06F1/04 ,  H03K3/0315 ,  H03K3/70

Abstract: A glitch free controlled ring oscillator comprising a programmable delay chain (1) connected to a gating and inverting means (3) wherein a latching means (2) is provided between said prgrammable delay chain (1) and said gating and inverting means (3) for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

公开(公告)号：EP1708080A1

公开(公告)日：2006-10-04

申请号：EP06111980.6

申请日：2006-03-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G06F5/10

CPC classification number: G06F5/10 ,  G06F2205/063

Abstract: The present invention provides a configurable length First-in First-out memory comprising a memory core for storing the data; a write address counter connected to said memory core for counting the locations for writing the data; and a read address counter connected to said memory core for counting the locations for reading the data wherein said read address counter includes a comparator for generating synchronous reset for said read address counter and a selection means connected to said comparator for selecting user defined FIFO length or pre-programmed write address counter length.

Abstract translation: 本发明提供了一种可配置长度的先进先出存储器，包括用于存储数据的存储器核心; 连接到所述存储器核心的写入地址计数器，用于对用于写入数据的位置进行计数; 以及连接到所述存储器核心的读地址计数器，用于对用于读取数据的位置进行计数，其中所述读地址计数器包括用于为所述读地址计数器产生同步复位的比较器，以及连接到所述比较器的选择装置，用于选择用户定义的FIFO长度或 预编程写地址计数器长度。

公开(公告)号：EP1672791A2

公开(公告)日：2006-06-21

申请号：EP05112285.1

申请日：2005-12-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Tiwari, Naveen ,  Singh, Balwant

IPC: H03K3/03

CPC classification number: G06F1/04 ,  H03K3/0315 ,  H03K3/70

Abstract: A glitch free controlled ring oscillator comprising a programmable delay chain connected to a gating and inverting means wherein a latching means is provided between said delay chain and said gating and inverting means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

Abstract translation: 一种无毛刺控制环形振荡器，包括连接到门控和反相装置（3）的可编程延迟链（1），其中在所述可编程延迟链（1）和所述选通和反相装置（3）之间提供锁存装置（2） 用于在禁止振荡器并将振荡器的输出设置为所述注册的时钟状态时注册时钟状态。

公开(公告)号：EP1585139A1

公开(公告)日：2005-10-12

申请号：EP05102753.0

申请日：2005-04-07

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bahl, Swapnil ,  Singh, Balwant

IPC: G11C29/00 ,  G01R31/317 ,  G01R31/3187

CPC classification number: G11C29/16 ,  G01R31/31724 ,  G11C29/006 ,  G11C29/12015 ,  G11C2029/1208 ,  G11C2029/5602

Abstract: An on-chip and at-speed testerfor testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localised Signal Generators located inside each memory block and controlled by said Centralized Flow Controlle for applying specified test patterns on the associated memory array.

Abstract translation: 一种用于在集成电路器件中测试和表征不同类型存储器的片上和速度测试器，其包括用于自动控制所选测试程序的测试操作的集中流量控制器和位于每个存储器块内的本地化信号发生器，并被控制 通过所述集中流控制器在相关联的存储器阵列上应用指定的测试图案。