公开(公告)号：WO2012085951A1

公开(公告)日：2012-06-28

申请号：PCT/IT2010/000511

申请日：2010-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation circuit (1) is described inserted between a connection node (HVout) to a matrix (2) of switches suitable for receiving a high voltage signal (IM) and a connection terminal (pzt) to a load (PZ) suitable for transmitting said high voltage signal (IM) to said load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, - Vss) and comprising at least a first driving transistor (M l), inserted, in series with a first driving diode (Dl), between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted, in series with a second diode (D2), between the driving central circuit node (Xc) and the second supply voltage reference (-Vss). The switch comprises an isolation block (8) connected to the connection terminal (pzt), to the connection node (HVout) and to the driving central circuit node (Xc) and comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the connection node (HVout) to the matrix (2) of switches and the connection terminal (pzt) to the load (PZ) of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc).

Abstract translation: 描述了一种低电压隔离电路（1），其插入到适于接收高电压信号（IM）的开关的矩阵（2）的连接节点（HVout）和适合于负载（PZ）的连接端子（pzt）之间 用于将所述高电压信号（IM）发送到包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5）的类型的所述负载（PZ），并且至少包括第一驱动晶体管 （M1）与第一驱动二极管（D1）串联插入在第一电压基准（Vss）和第一驱动中心电路节点（Xc）和第二驱动晶体管（M2）之间，然后插入 与驱动中心电路节点（Xc）和第二电源电压基准（-Vss）之间的第二二极管（D2）串联。 开关包括连接到连接端子（pzt）的隔离块（8），连接节点（HVout）和驱动中心电路节点（Xc），并且包括至少一个限压器块（6），二极管块 （7）和控制晶体管（MD），它们连接在连接节点（HVout）与开关矩阵（2）之间的二极管块（7）和连接端子（pzt）与负载（PZ）之间 低电压隔离开关（1）并具有连接到驱动中心电路节点（Xc）的控制端子（XD）。

公开(公告)号：WO2011079880A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005929

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio ,  GIOVANNONE, Juri

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/06 ,  H03K17/687 ,  B06B1/02 ,  H03K17/0812

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation switch (1) is described, inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting this high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) being inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (M1), inserted, in series to a first driving diode (D1), between the first voltage reference (Vss) and a first driving central circuit node (Xd) and a second driving transistor (M2), in turn inserted, in series with a second driving diode (D2), between the driving central circuit node (Xd) and the second supply voltage reference (-Vss) as well as a control transistor (MD) connected across a diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1), this control transistor (MD) having a control terminal connected to the driving central circuit node (Xd) through a low voltage decoupling block (6), in turn inserted between a first and a second substrate terminal (SS1, SS2) and also comprising a first and a second parasite capacitive element (Par1, Par2) connected to these first and second substrate terminals (SS1, SS2) as well as comprising at least one first decoupling transistor (M3) and one second decoupling transistor inserted (M4), being in parallel to each other and having control terminals connected to the first and second parasite capacitive elements (Par1, Par2), respectively.

Abstract translation: 描述了将低电压隔离开关（1）插入适于接收高电压信号（IM）的输入端（HVout）和适于将该高电压信号（IM）发送到负载的输出端（pzt）之间 PZ），其包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5），并且包括与第一驱动二极管串联插入的第一驱动晶体管（M1） D1），在第一电压基准（Vss）和第一驱动中心电路节点（Xd）和第二驱动晶体管（M2）之间，与第二驱动二极管（D2）串联插入驱动中心电路 节点（Xd）和第二电源电压参考（-Vss）以及连接在二极管块（7）之间的控制晶体管（MD），二极管块（7）包括至少一个第一和第二传输二极管（DN1，DN2），反相并联 即通过使第一二极管的阳极端子连接到阴极 在低电压隔离开关（1）的输入（HVout）和输出（pzt）端子之间，该控制晶体管（MD）具有连接到驱动中心电路节点的控制端（ Xd）通过低电压去耦块（6）进而插入在第一和第二衬底端子（SS1，SS2）之间，并且还包括连接到这些第一和第二衬底端子的第一和第二寄生电容元件（Par1，Par2） 衬底端子（SS1，SS2）以及包括彼此并联并具有连接到第一和第二寄生电容元件的控制端子的至少一个第一去耦晶体管（M3）和一个第二去耦晶体管（M4） Par1，Par2）。

公开(公告)号：EP3185415B1

公开(公告)日：2018-07-25

申请号：EP16172129.5

申请日：2016-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： SAUTTO, Marco ,  QUAGLIA, Fabio ,  RICOTTI, Giulio ,  MAZZANTI, Andrea

IPC: H03F3/00 ,  H03F3/45 ,  H03F3/217 ,  H03G1/00

CPC classification number: H03G1/0094 ,  H03F3/005 ,  H03F3/2175 ,  H03F3/45 ,  H03F3/45264 ,  H03F2200/312 ,  H03F2203/45288

Abstract: In an embodiment, a programmable-gain amplifier includes: two complementary cross-coupled transistor (e.g. MOS) pairs (M n-a , M n-b ; M p-a , M p-b ) mutually coupled with each transistor in one pair (M n-a resp. M n-b ) having a current flow path cascaded with a current flow path of a respective one of the transistors in the other pair (M p-a resp. M p-b ) to provide first (A) and second (B) coupling points between said complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ); first (C a ) and second (C b ) sampling capacitors set between the first (A) and second (B) coupling points, respectively, and ground; first (10) and second (12) input stages having input terminals for receiving input signals (V in- , V in+ ) for sampling by the first (C a ) and second (C b ) sampling capacitors. Switching means (201 to 206; 301, 302) are provided for: - i) coupling the first (10) and second (12) input stages to the first (C a ) and second (C b ) sampling capacitors, whereby the input signals (V in- , V in+ ) are sampled as sampled signals (V out+ , V out- ) on said first (C a ) and second (C b ) sampling capacitors, and - ii) energizing (V dd ) the complementary cross-coupled transistor pairs (M n-a , M n-b ; M p-a , M p-b ) whereby the signals (V out+ , V out- ) sampled on the first (C a ) and second (C b ) sampling capacitors undergo negative resistance regeneration growing exponentially over time, thereby providing an exponential amplifier gain.

公开(公告)号：EP4173729A1

公开(公告)日：2023-05-03

申请号：EP22203207.0

申请日：2022-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： GIUSTI, Domenico ,  QUAGLIA, Fabio ,  PRELINI, Carlo Luigi

IPC: B06B1/06

Abstract: PMUT acoustic transducer (10) formed in a body (11) of semiconductor material having a face (11A) and accommodating a plurality of first buried cavities (12A-12H), having an annular shape, arranged concentrically with each other and extending at a distance from the face (11A) of the body (11). The first buried cavities (12A-12H) delimit from below a plurality of first membranes (13A-13H) formed by the body (11) so that each first membrane (13A-13H) extends between a respective first buried cavity (12A-12H) of the plurality of first buried cavities and the face (11A) of the body (11). The plurality of first membranes (13A-13H) include a central membrane (13A) and a plurality of peripheral membranes (13B-13H) surrounding the central membrane (13A) and spaced outward in the radial direction. A plurality of piezoelectric elements (15A-15H) extend on the face of the body, each piezoelectric element extending above a respective first membrane (13A-13H) of the plurality of first membranes. The first membranes (13A-13H) have different widths (w1-w8), variable between a minimum value and a maximum value and define respective different resonance frequencies.

公开(公告)号：EP3530358A1

公开(公告)日：2019-08-28

申请号：EP19158949.8

申请日：2019-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： PROCOPIO, Francesco ,  QUAGLIA, Fabio

IPC: B06B1/02 ,  B06B1/06 ,  G10K9/125 ,  B81C1/00

Abstract: A device (51) for emitting an ultrasound acoustic wave (42) in a propagation medium, comprising: a package (50) including a base substrate (36) and a cap (38) coupled to the base substrate and defining therewith a chamber (40) in the package (50); a semiconductor die (35), coupled to the base substrate (36) in the chamber (40), comprising a semiconductor body (2); a micromachined ultrasonic transducer (MUT) (1; 30) integrated at least in part in the semiconductor body (2) and including a cavity (6; 32) in the semiconductor body (2) and a membrane (8) suspended over the cavity (6); and an actuator (18), operatively coupled to the membrane (8), which can be operated for generating a deflection of the membrane (8). The membrane (8) is designed in such a way that a resonance frequency (f 0 ) thereof matches an acoustic resonance frequency that, during operation of the MUT (1; 30), develops in said chamber (40) of the package (50) .

公开(公告)号：EP3238629A1

公开(公告)日：2017-11-01

申请号：EP16206869.6

申请日：2016-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： MORELLI, Marco ,  QUAGLIA, Fabio ,  TOIA, Fabrizio Fausto Renzo ,  SAMBI, Marco ,  BARILLARO, Giuseppe

IPC: A61B8/00 ,  G01N29/32 ,  B06B1/02 ,  H04R19/00

CPC classification number: B06B1/0292 ,  A61B8/4483 ,  B06B1/0644 ,  B06B1/067 ,  B06B1/0685 ,  G10K9/22 ,  G10K11/02 ,  H04R19/005

Abstract: The acoustic device has a micromachined acoustic transducer element (15); an acoustically attenuating region (40); and an acoustic matching region (32) arranged between the acoustic transducer element (15) and the acoustically attenuating region (40). The acoustic transducer element (15) is formed in a first substrate (25) housing a cavity (19) delimiting a membrane (16). A second substrate (30) of semiconductor material integrating an electronic circuit is arranged between the acoustic transducer element (15) and the acoustically attenuating region (40). The acoustic matching region (32) has a first interface (32A) with the second substrate (30) and a second interface (32B) with the acoustically attenuating region (40). The acoustic matching region (32) has an impedance matched to the impedance of the second substrate (30) in proximity of the first interface (32A), and an impedance matched to the acoustically attenuating region (40) in proximity of the second interface (32B).

Abstract translation: 声学装置具有微机械声学换能器元件（15）; 一个声学衰减区域（40）; 和布置在声学换能器元件（15）和声学衰减区域（40）之间的声学​​匹配区域（32）。 声换能器元件（15）形成在容纳界定膜（16）的空腔（19）的第一基板（25）中。 集成电子电路的半导体材料的第二衬底（30）布置在声学换能器元件（15）与声学衰减区域（40）之间。 声匹配区（32）具有与第二基板（30）的第一界面（32A）以及与声学衰减区（40）的第二界面（32B）。 声匹配区域（32）具有与第一接口（32A）附近的第二基板（30）的阻抗匹配的阻抗以及与第二接口（32A）附近的声学衰减区域（40）匹配的阻抗 32B）。

公开(公告)号：EP3599217A1

公开(公告)日：2020-01-29

申请号：EP19187949.3

申请日：2019-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： QUAGLIA, Fabio ,  FERRERA, Marco ,  DEL SARTO, Marco

IPC: B81C1/00

Abstract: A process for manufacturing MEMS devices (101), including the step of forming a first assembly (74), which comprises: a dielectric region (122); a redistribution region (128); and a plurality of unit portions (76). Each unit portion (76) of the first assembly (74) includes: a die (2, 4), arranged in the dielectric region; and a plurality of first and second connection elements (18, 20), which give out onto opposite faces of the redistribution region (128) and are connected together by means of paths (30, 32) that extend in the redistribution region (128), the first connection elements (18, 20) being coupled to the die (2, 4). The process further includes the steps of: forming a second assembly (80; 110), which comprises a plurality of respective unit portions (84; 284), each of which includes a semiconductor portion (82; 282) and third connection elements (36, 50); mechanically coupling the first and second assemblies (74, 80; 74, 110) so as to connect the third connection elements (36, 50) to corresponding second connection elements (34); and then removing at least part of the semiconductor portion (82; 282) of each unit portion (84; 284) of the second assembly (80; 110), thus forming corresponding membranes (40).

公开(公告)号：EP3025792B1

公开(公告)日：2019-09-04

申请号：EP15196387.3

申请日：2015-11-25

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSI, Sandro ,  GHISU, Davide Ugo ,  QUAGLIA, Fabio ,  LEONE, Antonio Davide

IPC: B06B1/02 ,  G05F3/02 ,  H03K4/94

公开(公告)号：EP4378883A1

公开(公告)日：2024-06-05

申请号：EP23207483.1

申请日：2023-11-02

Applicant: STMicroelectronics S.r.l.

Inventor： GIUSTI, Domenico ,  QUAGLIA, Fabio ,  FERRERA, Marco ,  PRELINI, Carlo Luigi ,  SAVOIA, Alessandro Stuart

IPC: B81C1/00

CPC classification number: B81C1/00238 ,  B81C2203/079220130101

Abstract: MEMS device (1) comprising: a signal processing assembly (120); a transduction module (38; 40, 41, 56) comprising a plurality of transducer devices (56); a stiffening structure (113) at least partially surrounding each transducer device (56); one or more coupling pillars (36) for each transducer device (56), extending on the stiffening structure (113) and configured to physically and electrically couple the transduction module (38; 40, 41, 56) to the signal processing assembly (120), to carry control signals of the transducer devices (56). Each conductive coupling element (36) has a section having a shape such as to maximize the overlapping surface with the stiffening structure (113) around the respective transducer device (56). This shape includes hypocycloid with a number of cusps equal to or greater than three; triangular; quadrangular.

公开(公告)号：EP4361625A1

公开(公告)日：2024-05-01

申请号：EP23202590.8

申请日：2023-10-10

Applicant: STMicroelectronics S.r.l.

Inventor： GIUSTI, Domenico ,  DEL SARTO, Marco ,  QUAGLIA, Fabio ,  DUQI, Enri

IPC: G01N29/04 ,  G01N29/07 ,  G01N29/11

CPC classification number: G01N29/043 ,  G01N29/07 ,  G01N29/11 ,  G01N2291/269720130101 ,  G01N2291/025820130101 ,  G01N2291/04420130101 ,  G01N2291/10120130101 ,  G01N2291/10620130101

Abstract: An integrated electronic system (1) is provided with a package (2) formed by a support base (4) and a coating region (5) arranged on the support base (4) and having at least a first system die (6), including semiconductor material, coupled to the support base (4) and arranged in the coating region (5). The integrated electronic system also has, within the package (2), a monitoring system (14) configured to determine the onset of defects within the coating region (5), through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.