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    Method for the uniform distribution of additional signal clocks
    3.
    发明公开
    Method for the uniform distribution of additional signal clocks 审中-公开
    Methodefürdie uniforme VerteilungzusätzlicherSignaltakte

    公开(公告)号：EP1160660A1

    公开(公告)日：2001-12-05

    申请号：EP00830397.6

    申请日：2000-06-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bardelli, Roberto

    IPC: G06F7/68

    CPC classification number: G06F7/68

    Abstract: The present invention relates a method for the subdivision of a period (T c ) for the uniform distribution of additional signal clocks, characterised in that it comprises a plurality of steps wherein a number ADJ of signal clocks are added every 2 i subperiods in function of the most significant bit in said vector (ADJ) and in function of the least significant bit in said counter (AC).

    Abstract translation: 本发明涉及一种用于细分附加信号时钟的均匀分布的周期（Tc）的方法，其特征在于它包括多个步骤，其中信号时钟的数量ADJ在功能上每2个子周期相加 （ADJ）中的最高有效位和所述计数器（AC）中的最低有效位的功能。

    Successive-approximation analog-digital converter and related operating method
    5.
    发明公开
    Successive-approximation analog-digital converter and related operating method 有权
    模拟数字万用表schrittweiserAnnäherungund entsprechendes Betriebsverfahren

    公开(公告)号：EP1150432A1

    公开(公告)日：2001-10-31

    申请号：EP00830311.7

    申请日：2000-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bardelli, Roberto ,  Tarantola, Mario

    IPC: H03M1/08

    CPC classification number: H03M1/08 ,  H03M1/462

    Abstract: Herein described is a successive-approximation analog-digital converter comprising a logic control circuit (1) timed by means of an external clock signal (clock). Said logic control circuit (1) comprises a register (11), which contains a first digital signal (D1) formed of N bits and obtained from a first analog-digital conversion. Said control circuit (1) is suitable for producing a second digital signal (D) formed of N bits through a second analog-digital conversion in N clock cycles. Said analog-digital converter comprises a digital-analog converter (2) which converts the second digital signal (D) sent by the logic circuit (1) to an analog signal (A), a comparator (3) which compares the analog signal (A) with an analog signal (B) which is in input to the analog-digital converter. The converter comprises a device (20, 4) which enables the increase of the analog signal (A) in output from the digital-analog converter (2) and in input to the comparator (3) of a preset value (Voffs) when the bit of the first digital signal (D1) which corresponds in position to the bit of the second digital signal (D) which must be decided in a clock cycle is zero.

    Abstract translation: 这里描述的是包括通过外部时钟信号（时钟）定时的逻辑控制电路（1）的逐次逼近模数转换器。 所述逻辑控制电路（1）包括寄存器（11），其包含由N位形成并由第一模数转换获得的第一数字信号（D1）。 所述控制电路（1）适于通过N个时钟周期中的第二模拟数字转换产生由N位形成的第二数字信号（D）。 所述模拟数字转换器包括将由逻辑电路（1）发送的第二数字信号（D）转换为模拟信号（A）的数模转换器（2），将模拟信号 A）与模数转换器输入的模拟信号（B）。 该转换器包括一个器件（20,4），当器件（20,4）能够在数字模拟转换器（2）的输出中增加模拟信号（A），并且当输入到比较器（3）时，其输入为预设值（Voffs） 在与时钟周期中必须决定的第二数字信号（D）的位相对应的第一数字信号（D1）的位为零。

    Frequency multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor
    7.
    发明公开
    Frequency multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor 有权
    电路，用于倍频并使用在子周期期间的时间交织的无刷马达此电路的方法

    公开(公告)号：EP1160659A1

    公开(公告)日：2001-12-05

    申请号：EP00830396.8

    申请日：2000-06-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bardelli, Roberto

    IPC: G06F7/68

    CPC classification number: G06F7/68

    Abstract: The present invention relates a frequency multiplier circuit and a controlling method thereof, characterised in that it measures a period (T c ) of a waveform by a fixed frequency timing signal (f sys ), and that it reproduces said period (T c ) by approaching a number of prefixed length (T sys ) subperiods as equal as possible to each other so to minimise the reproduction error (ε) thanks to the interpretation of said subperiod number (m) in the following manner m = j * 2 i .

    Abstract translation: 本发明涉及一个频率倍增器电路和控制方法，它DASS测量由固定频率定时信号（FSYS）一个波形的周期（TC），并没有它通过接近若干再现所述周期（TC） 前缀长度（TSYS）的子周期尽可能等于海誓山盟所以最小化以下面的方式米= j的* 2的再现误差（ε）得益于说子周期数目（M）的解释的。

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