公开(公告)号：EP1139210A1

公开(公告)日：2001-10-04

申请号：EP00830228.3

申请日：2000-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rocchi, Alessandro ,  Bisio, Marco ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

Abstract: An architecture of a FLASH memory organized in a plurality of physical sectors wherein read, write and erase operations of data occupying a fractional memory space of any one of said physical sectors are carried out, may include splitting a physical sector in a plurality of singularly addressable logic sectors. Each logic sector (j) is defined by a memory space of pre-established size (PAYLOAD j ), a chain pointer (CHAIN_PTR j ) assuming a neutral value (NULL) or a value pointing directly or indirectly to a second logic sector associated to a respective chain pointer (CHAIN_PTR 2 ) at neutral value (NULL), a status indicator (STATUS j ) assuming a first value (FREE) if the logic sector is empty, a second value (OD) if the data contained in it belongs to the logic sector, a third value (NOD) if the data do not belong to the logic sector, or a fourth value (DEL) if the data has been erased, and a remap pointer (REMAP_PTR j ) assuming the neutral value (NULL) or a value pointing directly or indirectly to the chain pointer (CHAIN_PTR 3 ) of a third logic sector.
A further improvement consists in attributing to each physical sector a logical address (LOGICAL_ADDRESS) permitting to destine to the function of temporary buffer, for partly erasing the content of a physical sector, in rotation all the physical sectors, not to repeatedly stressing the same sector.

Abstract translation: 组织在多个物理扇区中的FLASH存储器的架构，其中执行占用任何一个所述物理扇区的分数存储器空间的数据的读，写和擦除操作，包括分割多个可单独寻址的物理扇区 逻辑部门。 每个逻辑扇区（j）由预先确定的大小（PAYLOADj）的存储器空间，假定中性值（NULL）的链指针（CHAIN_PTRj）或直接或间接指向与相应的第二逻辑扇区 链路指针（CHAIN_PTR2）为中性值（NULL），如果逻辑扇区为空则假定为第一值（FREE）的状态指示符（STATUSj），如果其中包含的数据属于逻辑扇区，则为第二值（OD） 如果数据不属于逻辑扇区，则为第三值（NOD），如果数据已经被擦除则为第四值（DEL），以及假设中性值（NULL）或直接指向的值的重映射指针（REMAP_PTRj） 或间接地连接到第三逻辑扇区的链指针（CHAIN_PTR3）。 进一步的改进在于将归属于每个物理扇区的逻辑地址（LOGICAL_ADDRESS）允许指定临时缓冲区的功能，以部分地擦除物理扇区的内容，旋转所有物理扇区，而不是反复强调同一扇区 。

公开(公告)号：EP1139210B1

公开(公告)日：2004-03-17

申请号：EP00830228.3

申请日：2000-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rocchi, Alessandro ,  Bisio, Marco ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

公开(公告)号：EP1126466A1

公开(公告)日：2001-08-22

申请号：EP00830115.2

申请日：2000-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Borgatti, Michele ,  Rocchi, Alessandro ,  Bisio, Marco ,  Rolandi, Pierluigi ,  Pasotti, Marco

IPC: G11C7/16 ,  G06F12/02 ,  G06F3/16

CPC classification number: G11C7/16 ,  G06F3/16 ,  G06F12/023 ,  G11B20/00007 ,  G11B20/10527 ,  G11B2020/10685

Abstract: The electronic device (1) is integrated in a chip (50) of semiconductor material, and comprises a control unit (3), a signal-conversion unit (4), and a non-volatile memory unit (5), which are connected together via a main transmission line (6). The signal-conversion unit (4) is designed to receive at input an analog signal correlated to a voice signal, and to generate at output a stream of appropriately compressed digital signals. The stream of compressed digital signals is then stored in pre-set memory locations of the non-volatile memory unit (5) according to the control signals generated by the control unit (3). During reproduction, the compressed digital signals stored in the non-volatile memory unit (5) are supplied to the signal-conversion unit (4), which decompresses them and sends them to a loudspeaker (43).

Abstract translation: 所述电子设备（1）集成在半导体材料的芯片（50），并且包括一个控制单元（3），信号转换单元（4），和非易失性存储器单元（5），其连接 一起经由主传输线（6）。 所述信号转换单元（4）被设计为接收在输入到相关的语音信号的模拟信号，并在输出端适当地产生压缩的数字信号流。 然后被压缩的数字信号的数据流被存储在非易失性存储器单元（5）的预设置的存储器位置雅丁到由控制单元产生的控制信号（3）。 在再现期间，存储在所述非易失性存储器单元（5）的压缩数字信号被提供给信号转换单元（4），该解压缩它们，并将它们发送到扬声器（43）。

公开(公告)号：EP0980187A1

公开(公告)日：2000-02-16

申请号：EP98830493.7

申请日：1998-08-10

Applicant: STMicroelectronics S.r.l.

Inventor： Bisio, Marco ,  Rambaldi, Roberto ,  Guerrieri, Roberto

IPC: H04N9/04

CPC classification number: H04N9/045 ,  H04N2209/046

Abstract: An interpolation method (200) for obtaining a digital image constituted by a matrix of elements each comprising at least one colour component representative of an elemental area of the image includes the steps of providing (210) an incomplete digital image having at least one incomplete element in which at least one colour component is missing, each missing colour component in each incomplete element being present in opposed elements disposed on opposite sides of the incomplete element along at least one direction, determining (230), for each missing colour component of each incomplete element, an interpolation direction in which a variation of the corresponding colour components of the opposed elements is least, and setting (235) the missing colour component at a value equal to a mean of the corresponding colour components of the opposed elements along the interpolation direction.

Abstract translation: 一种用于获得由每个包括表示图像的基本区域的至少一个颜色分量的元素矩阵构成的数字图像的插值方法（200），包括以下步骤：提供（210）具有至少一个不完整元素的不完整数字图像 其中缺少至少一个颜色分量，每个不完整元素中的每个缺失颜色分量存在于沿着至少一个方向设置在不完整元素的相对侧上的相对元件中，对于每个不完整元素的每个缺失颜色分量，确定（230） 元素，其中相对元素的相应颜色分量的变化最小的插值方向，并且将缺失颜色分量设置（235）为等于相对元素沿插值方向的相应颜色分量的平均值 。