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    Architecture for reconfigurable digital signal processor
    2.
    发明公开
    Architecture for reconfigurable digital signal processor 审中-公开
    建筑师建筑师Digecignalprozessor

    公开(公告)号：EP1443418A1

    公开(公告)日：2004-08-04

    申请号：EP03425055.5

    申请日：2003-01-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campi, Fabio ,  Toma, Mario ,  Lodi, Andrea ,  Cappelli, Andrea ,  Canegallo, Roberto ,  Guerrieri, Roberto

    IPC: G06F15/78 ,  G06F9/38

    CPC classification number: G06F9/3885 ,  G06F9/3877 ,  G06F9/3897 ,  G06F15/7867

    Abstract: The present invention relates to digital embedded architecture (1), including a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor (2), structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel (5, 6) comprising a reconfigurable function unit based on a pipelined array (7) of configurable look-up table based cells controlled by a special purpose control unit (8), thus easing the elaboration of critical kernels algorithms.

    Abstract translation: 本发明涉及一种数字嵌入式架构（1），包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，包括：处理器（2），其被构造为通过一般的实现非常长的指令字精炼模式 以及包括基于由专用控制单元（8）控制的基于可配置的查找表的单元的流水线阵列（7）的可重新配置功能单元（5,6）的附加数据精细化通道（5,6），从而缓解 阐述关键内核算法。

    Chip-to-chip communication system
    4.
    发明公开
    Chip-to-chip communication system 有权
    芯片到芯片通信系统

    公开(公告)号：EP1762943A8

    公开(公告)日：2007-10-10

    申请号：EP05019644.3

    申请日：2005-09-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Magagni, Luca ,  Fazzi, Alberto ,  Canegallo, Roberto ,  Guerrieri, Roberto

    IPC: G06F13/40

    CPC classification number: H01L25/0657 ,  G06F13/4077 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to a chip-to-chip communication system (10) of the type comprising at least a transmitter TX (11) and a receiver RX (12), inserted between a first and a second voltage references (Vdd, GND) and connected to respective transmitter and receiver clock terminal wherein respective transmitter and receiver clock signals (CP, G) are applied, the transmitter TX (11) having an input terminal (TXin) receiving an input data (D) and an output terminal (TXout) connected to an input terminal (RXin) of the receiver RX (12) at a connection block (15), the receiver RX (12) having an output terminal (RXout) issuing an output signal (Q).
    Advantageously according to the invention:
    - the transmitter TX (11) comprises at least a precharge and an evaluation blocks (18, 19) connected to each other and to the transmitter clock terminal (CP);
    - the receiver RX (12) comprises at least a precharge block (25) connected to the receiver clock terminal (G)

    the precharge blocks (18, 25) precharging the output terminal (TXout) of the transmitter TX (11) and the input terminal (RXin) of the receiver RX (12), respectively, to a value corresponding to a first voltage reference (Vcc) during a low phase of the transmitter clock signal (CP).

    Texile-like capacitive pressure sensor and method of mapping the pressure exerted at points of a surface of a flexible and pliable object, particularly of a sail
    7.
    发明公开
    Texile-like capacitive pressure sensor and method of mapping the pressure exerted at points of a surface of a flexible and pliable object, particularly of a sail 有权
    纺织型电容式压力传感器和用于柔性和柔韧物体的表面上的映射点压力的方法，特别是施加帆

    公开(公告)号：EP1211633A1

    公开(公告)日：2002-06-05

    申请号：EP00830779.5

    申请日：2000-11-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manaresi, Nicolo ,  Tartagni, Marco ,  Monnier, Joel ,  Guerrieri, Roberto

    IPC: G06K11/16 ,  B63B17/00 ,  G01L1/14

    CPC classification number: G06F3/044 ,  B63H9/06 ,  G01L1/146 ,  G06F3/0414 ,  G06F2203/04102

    Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, comprises a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors constituted by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dieletric, constituting an array of pressure sensing pixel capacitors. Further described is a method of trimming a sail for maximizing the net thrust on the windward face of the sail based on instrumentally reconstructing distribution maps of the pressure over the sail area in real time and with a certain frame rate.

    Abstract translation: 一种用于检测压力装置施加在柔性的和/或柔韧的对象的不同点也可以采取不同的形状，包括电容压力传感器的多元性和至少用于偏置和读出传感器的电容的系统。 的柔韧性或柔软性的要求通过由两组正交间隔开，至少在一组的电极之间的每一个交叉，与另一组的电极，通过在弹性可压缩dieletric平行或基本平行的电极构成电容压力传感器满足， 构成压力检测像素电容器的阵列组成。 进一步描述的是修整帆对帆的迎风面最大化净推力的基础上用仪器随重构在实时和以一定的帧速率的帆区域上的压力的分布图的方法。

    Communication system between independently clocked devices
    8.
    发明公开
    Communication system between independently clocked devices 有权
    公民社会革命

    公开(公告)号：EP2075708A2

    公开(公告)日：2009-07-01

    申请号：EP08022446.2

    申请日：2008-12-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

    IPC: G06F13/40

    CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

    Abstract: The invention relates to a communication system for the connection between timing non correlated synchronous devices of the type comprising at least one transmitter (30) and one receiver (40) inserted between a first and a second voltage reference (Vcc, GND) and connected to each other by means of a transmitting channel (25) in correspondence with respective transmitting (TX) and receiving (RX) terminals. Advantageously according to the invention, the receiver (40) comprises at least one synchronous input stage (41) suitable for receiving on said receiving terminal (RX) a datum (D) and associated with a synchronous output stage (42) suitable for transmitting said datum (D) in a synchronised way with a clock signal (CP) on a synchronised receiving terminal (RXs).
    The invention also relates to a method for transmitting a datum (D) from a transmitter (30) to a receiver (40) interconnected by means of a capacitive channel (25) in a communication system for the connection between independently clocked devices.

    Abstract translation: 本发明涉及一种用于在包括至少一个发射器（30）和插入在第一和第二电压参考（Vcc，GND）之间的一个接收器（40）的类型的定时非相关同步装置之间的连接的通信系统，并且连接到 彼此通过与相应的发送（TX）和接收（RX）终端相对应的电容或电阻信道（25）来实现。 有利地，根据本发明，接收器（40）包括适于在所述接收终端（RX）上接收数据（D）的至少一个同步输入级（41）并与适于发送所述接收器（40）的同步输出级（42）相关联的至少一个同步输入级 数据（D）以与同步接收终端（RX）上的时钟信号（CP）同步的方式。

    Communication system between first and second independently clocked devices
    9.
    发明公开
    Communication system between first and second independently clocked devices 有权
    一个第一和一个第二独立计数设备之间的通信系统

    公开(公告)号：EP2075710A2

    公开(公告)日：2009-07-01

    申请号：EP08022447.0

    申请日：2008-12-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

    IPC: G06F13/42

    CPC classification number: H04L7/10 ,  H04L7/0037

    Abstract: The invention relates to a communication system between a first and a second independently clocked devices (L,R), in particular chips, comprising, for each device, at least a transmitter (TXL,TXR) and a receiver (RXL,RXR) connected to each other in a crossed way in correspondence of an inter-chip communication channel (ICC). Advantageously according to the invention, the communication system further comprises a synchronizer (40) in turn including at least a first and a second synchronization block (20L,20R), having respective input terminals (INrL,INrR) connected to the receivers (RXL,RXR) and respective output terminals (OUTtL,OUTtR) connected to the transmitters (TXL,TXR) and comprising at least:
    - a test pattern generator (23);
    - comparison means (21,22) to check a matching between stored and received test pattern signals; and
    - a delay block (26) able to change the clock phases.

    Abstract translation: 本发明涉及到一个第一和一个第二unabhängig时钟控制装置（L，R）之间的通信系统，特别是芯片，其包括，对于每一个设备，至少一个发送器（TXL，TXR）和接收器（RXL，RXR）连接 海誓山盟在一个芯片间通信信道（ICC）的对应关系的交叉方法。 有利的是雅丁到本发明，该通信系统还包括又一个同步器（40）包括至少一个第一和一个第二同步块（20L，20R），其具有连接到所述接收器respectivement输入端子（INrL，INRR）（RXL， RXR）和相应的输出端子连接到所述发射机（TXL，TXR）和包含至少（OUTtL，OUTtR）： - 测试图案生成器（23）; - 比较装置（21,22），以检查存储和接收的测试模式信号之间的匹配; 和 - 一个延迟块（26），其能够改变时钟相位。

    Asynchronous interconnection system for 3D inter-chip communication
    10.
    发明公开
    Asynchronous interconnection system for 3D inter-chip communication 有权
    不同步的Verbindungssystemfür3D-Inter-Chip-Kommunikation

    公开(公告)号：EP1940028A1

    公开(公告)日：2008-07-02

    申请号：EP06027047.7

    申请日：2006-12-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fazzi, Alberto ,  Guerrieri, Roberto ,  Magagni, Luca ,  Ciccarelli, Luca ,  Canegallo, Roberto

    IPC: H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/018521 ,  H03K3/356165

    Abstract: The present invention relates to a asynchronous interconnection system (10) comprising a transmitter circuit (11) and a receiver circuit (12) inserted between inserted between respective first and second voltage references (Vcctx, GNDtx - Vccrx, GNDrx) and having respective transmitter and receiver nodes (TX, RX) coupled in a capacitive manner.
    Advantageously according to the invention, the receiver circuit (12) comprises:
    - a recovery stage (13) inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) and connected to the receiver node (RX); and
    - a state control stage (14), in turn inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) connected to the recovery stage (13) correspondence with a first feedback node (X) providing a first control signal (Recovery Enable) and having a second feedback node (Z*) connected in a feedback manner to the recovery stage (13).
    The recovery stage (13) comprises a first feedback loop (Loop 1) connected to the first feedback node (X) and acting in such a way to recover a received voltage signal and a feedback loop (Loop2) connected to the second feedback node (Z*) of the state control stage (14) and acting in such a way to deactivate the recovery feedback on the receiver node (RX) and guarantee that the receiver node (RX) is let in a high impedance state.

    Abstract translation: 本发明涉及一种异步互连系统（10），包括发射机电路（11）和插入在相应的第一和第二电压基准（Vcctx，GNDtx-Vccrx，GNDrx）之间的接收机电路（12），并且具有各自的发射机和 接收器节点（TX，RX）以电容方式耦合。 有利地，根据本发明，接收器电路（12）包括： - 插入在接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间并连接到接收器节点（RX）的恢复级（13） ; 以及 - 状态控制级（14），其又插入在与恢复级（13）连接的接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间，与第一反馈节点（X）对应，提供 第一控制信号（恢复使能）并且具有以反馈方式连接到恢复级（13）的第二反馈节点（Z *）。 恢复阶段（13）包括连接到第一反馈节点（X）的第一反馈回路（回路1），并以这样一种方式起作用以恢复接收的电压信号和连接到第二反馈节点的反馈回路（Loop2） 状态控制级（14）的Z *），并以这样一种方式使接收器节点（RX）上的恢复反馈失效，并保证接收器节点（RX）处于高阻抗状态。

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