公开(公告)号：EP4156000A1

公开(公告)日：2023-03-29

申请号：EP22195518.0

申请日：2022-09-14

Applicant: STMicroelectronics S.r.l.

Inventor： MONDELLO, Antonino ,  CARRANO, Michele Alessandro ,  CONDORELLI, Riccardo

IPC: G06F21/57 ,  G06F21/64

Abstract: The present disclosure relates to a method comprising:
- executing, by an electronic device (100), a first firmware stored in a volatile memory (113) of the electronic device, the execution of the first firmware causing an updated firmware key (130) to be stored in a non-volatile memory (124) of the electronic device;
- uploading a second encrypted firmware module to the electronic device;
- decrypting the second encrypted firmware module by a cryptographic processor (108) of the electronic device based on the updated firmware key; and
- installing the decrypted second firmware module in the volatile memory of the electronic device at least partially overwriting the first firmware.

公开(公告)号：EP3557740B1

公开(公告)日：2020-11-11

申请号：EP19167171.8

申请日：2019-04-03

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (ALPS) SAS

Inventor： DRUILHE, Francois ,  ARNO, Patrik ,  INGLESE, Alessandro ,  CARRANO, Michele Alessandro

IPC: H02M1/36 ,  H02J1/10

公开(公告)号：EP4258550A1

公开(公告)日：2023-10-11

申请号：EP23161658.2

申请日：2023-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： CONDORELLI, Riccardo ,  CARRANO, Michele Alessandro ,  MONDELLO, Antonino

IPC: H03K5/26 ,  H03L7/091

Abstract: A method, comprising: producing (12) a set of delayed replicas (REF_D) of a reference clock signal (REF), wherein delayed replicas in the set of delayed replicas (REF_D) have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas (REF_D) from an edge of a clock signal (CK) having a clock period; selecting (16) based on edge detecting signals in the set of edge detecting signals a delayed replica (REF_Dj) in the set of delayed replicas (REF_D) having a distance from the clock signal edge (CK) that is shorter than the distance from the clock signal edge (CK) of any other delayed replica in the set of delayed replicas (REF_D); performing a comparison (18) of the clock period of the clock signal (CK) and of the selected delayed replica, obtaining as a result of the comparison, an error signal (CK_C) indicative of a difference therebetween, and providing the error signal (CK_C) to user circuitry (U) configured to calibrate the clock signal (CK) based on the error signal (CK_C).

公开(公告)号：EP3139275A1

公开(公告)日：2017-03-08

申请号：EP16162366.5

申请日：2016-03-24

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  CARRANO, Michele Alessandro ,  DISTEFANO, Gaetano ,  FRIED, Antonin

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

Abstract: In an embodiment, a method of managing memories (10) includes:
- providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition,
- writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and
- selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where:
- in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11),
- in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).

Abstract translation: 在实施例中，管理存储器（10）的方法包括： - 提供第一（11）存储器模块和第二存储器模块（12）每个都包括第一（R1，R2）和第二（R4，R3）的分区， - 在所述第一分区中的第一存储器模块的（R 1）（11）和在所述第一分区中的第二存储器模块的（R 2）（12）的第二数据（DATA2）写入第一数据（DATA1），以及 - 选择性地操作所述第一 （11）和第二在第一操作模式或第二操作模式，其中，（12）的存储器模块： - 在第一操作模式中，对于第一数据的奇偶校验位（PAR1）（DATA1）被写入到第二分区（R3 ）所述第二存储器模块（12）和用于所述第二数据的奇偶校验位（PAR2）（DATA2）的被写入到第二分区中的第一存储器模块的（R4）（11） - （在第二操作模式中，进一步的数据 ED1，ED2）被写入在一个或两个所述第一存储器模块（11的在第二分区中的奇偶校验位（PAR1，PAR2）（R4，R3））和所述第二存储器模块的地方 （12）。