公开(公告)号：EP1089453A1

公开(公告)日：2001-04-04

申请号：EP99830618.7

申请日：1999-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Cantone, Giuseppe ,  Cappelletti, Roberto

IPC: H04B3/54 ,  H04B3/56

CPC classification number: H04B3/56 ,  H04B3/54 ,  H04B2203/5425 ,  H04B2203/5483 ,  H04B2203/5495 ,  Y10T307/422

Abstract: The level of the signal output by a transceiver of digital information coupled to a power distribution line during a transmission phase is regulated by comparing the current level (Iref) of said output signal with a pre-established minimum threshold (IL) and a pre-established maximum threshold (IH); reducing the current level (Iref) when said maximum threshold (IH) is exceeded by reducing the gain; and passing to a voltage mode control of said output signal when the current level (Iref) of the output signal becomes lower than said minimum threshold (IL).
The architecture of a coupling interface implementing the above method is illustrated.

Abstract translation: 通过的过程中的传输相位耦合到配电线的数字信息的收发器输出的信号的电平是由所述输出信号的电流电平（IREF）与预先建立的最小阈值（IL）和预调节比较 建立的最大阈值（1H）; 降低电流电平（IREF）当通过降低增益超过所述最大阈值（1H）; 并传递到所述输出信号的电压模式控制，当输出信号的电流电平（IREF）变为大于所述最小阈值（IL）下。 一个耦合接口实现上述方法的结构中示出。

公开(公告)号：EP1096695B1

公开(公告)日：2012-03-21

申请号：EP99830680.7

申请日：1999-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Roberto ,  Cantone, Giuseppe

IPC: H04B3/54

CPC classification number: H04B3/54 ,  H04B2203/5408 ,  H04B2203/542 ,  H04B2203/5437 ,  H04B2203/5458 ,  H04B2203/5483 ,  H04B2203/5491

公开(公告)号：EP1835635A2

公开(公告)日：2007-09-19

申请号：EP07104200.6

申请日：2007-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Saggini, Stefano ,  Cappelletti, Roberto ,  Stefanutti, Walter ,  Mattavelli, Paolo

IPC: H04B3/54

CPC classification number: H04B3/548 ,  H04B2203/5425 ,  H04B2203/547 ,  H04B2203/5483 ,  H04B2203/5491 ,  Y10T307/685

Abstract: A transmitting apparatus of digital signals on a line (1) is disclosed, wherein there is a supply signal (Vbus) of electronic devices. Said apparatus comprises at least a direct-voltage switching converter (21) and means (3) suitable for varying the switching frequency of said converter (21) on the basis of a preset digital signal (Dig) to be transmitted; the converter is suitable for generating an alternating current signal (Salt) associated with the supply signal (Vbus) during the switching periods. The apparatus comprises further means (10) suitable for receiving said alternating current signal and suitable for processing the latter to obtain the preset digital signal (Dig).,1).

Abstract translation: 数字信号的一个线（1）的发送装置是游离缺失盘，worin有电子设备的电源信号（VBUS）。 所述装置包括至少一个直接电压开关转换器（21）和装置（3）适于在预设数字信号（DIG）的基础上改变所述转换器（21）的开关频率是反式mitted; 所述转换器适合于在交替期间开关周期与供给信号（VBUS）相关联的电流信号（盐）产生。 所述设备包括另外的装置（10）适于接收所述交流电流信号，并且适合于处理后者得到预置数字信号（DIG），1）。

公开(公告)号：EP1096695A1

公开(公告)日：2001-05-02

申请号：EP99830680.7

申请日：1999-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Roberto ,  Cantone, Giuseppe

IPC: H04B3/54

CPC classification number: H04B3/54 ,  H04B2203/5408 ,  H04B2203/542 ,  H04B2203/5437 ,  H04B2203/5458 ,  H04B2203/5483 ,  H04B2203/5491

Abstract: A data transceiving station of digital data frames comprising a digital modem (MODEM) coupled to a transmission line, a microprocessor (µP) receiving demodulated data from said modem according to a Packet Mode or a Bit Mode transmission through an interface circuit (SERIAL_INTERFACE) that switches from a Packet Mode to a Bit Mode transmission and/or viceversa during transfer of a data frame to said microprocessor conjugating the superior speed of a Packet Mode transfer with the unlimited compatibility of a Bit Mode transfer.

Abstract translation: 数字数据帧的数据收发站包括耦合到传输线的数字调制解调器（MODEM），微处理器（mu P）根据分组模式或通过接口电路（SERIAL_INTERFACE）的位模式传输从所述调制解调器接收解调数据， 在将数据帧传输到所述微处理器时，从分组模式切换到比特模式传输和/或反转，所述微处理器将分组模式传输的优越速度与位模式传输的无限兼容性相结合。