公开(公告)号：EP1601100A1

公开(公告)日：2005-11-30

申请号：EP04425383.9

申请日：2004-05-27

Applicant: STMicroelectronics S.r.l.

Inventor： Filoramo, Pietro ,  Cavallaro, Alberto Giuseppe

IPC: H03F3/45

CPC classification number: H03F3/45237 ,  H03F3/45708

Abstract: Herein described is an amplifying stage comprising a first circuit part (1) and a second circuit part (2). The first circuit part (1) is positioned between a first (Vdd) and a second reference voltage and comprises at least a first transistor (Ma1....Man) having a first non-drivable terminal connected with current supplying means (Ibias) and at least a second transistor (Mt1) having a first non-drivable terminal connected with a second non-drivable terminal of the at least a first transistor (Ma1....Man); the current supplying means (Ibias) are connected to said first reference voltage (Vdd). The second circuit part (2) is connected by circuit to the first circuit part (1) and is fed by a current (It2) proportional to the current supplied by the current supplying means (Ibias). The second circuit part (2) has at least one input terminal and is connected to a load (LOAD). The first circuit part (1) comprises means (3) for connecting said first non-drivable terminal of the at least a first transistor (Ma1....Man) with the drivable terminal of the at least a second transistor (Mt1) and said connection means (3) are suitable for imposing the current that passes through said at least a second transistor (Mt1) to be the same as current (Ibias) supplied by said current supplying means and the voltage (Vp) between said first non-drivable terminal of the at least a first transistor (Ma1....Man) and ground is greater than the saturation voltage (Vds-sat) between the non-drivable terminals of said at least a first transistor (Ma1....Man). At the drivable terminal of the at least a first transistor (Ma1....Man) and at the at least one input terminal of the second circuit part (2) the same at least one input signal (Vin1....Vinn).

Abstract translation: 这里描述的是包括第一电路部分（1）和第二电路部分（2）的放大级。 第一电路部分（1）位于第一（Vdd）和第二参考电压之间，并且至少包括具有与电流供应装置（Ibias）连接的第一不可驱动端子的第一晶体管（Ma1 ... Man） 以及至少第二晶体管（Mt1），具有与所述至少第一晶体管（Ma1 ... Man）的第二不可驱动端子连接的第一不可驱动端子。 电流供给装置（Ibias）连接到所述第一参考电压（Vdd）。 第二电路部分（2）通过电路连接到第一电路部分（1），并由与电流供应装置（Ibias）提供的电流成比例的电流（It2）馈送。 第二电路部分（2）具有至少一个输入端子并连接到负载（LOAD）。 第一电路部分（1）包括用于将至少第一晶体管（Ma1 ... Man）的所述第一不可驱动端子与至少第二晶体管（Mt1）的可驱动端子连接的装置（3）和 所述连接装置（3）适于将通过所述至少第二晶体管（Mt1）的电流施加到与所述电流供应装置提供的电流（Ibias）相同的电流和所述第一非易失性存储器之间的电压（Vp） 所述至少第一晶体管（Ma1 ... Man）和地的可驱动端子大于所述至少第一晶体管（Ma1 .... Man）的不可驱动端子之间的饱和电压（Vds-sat） ）。 在至少第一晶体管（Ma1 ... Man）的可驱动端子处和在第二电路部分（2）的至少一个输入端子处，相同的至少一个输入信号（Vin1 ... Vinn） 。