公开(公告)号：EP1677348A1

公开(公告)日：2006-07-05

申请号：EP05028380.3

申请日：2005-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pavan, Alessia ,  Servalli, Giorgio ,  Clementi, Gesare

IPC: H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: Method for manufacturing non volatile memory devices integrated on a semiconductor substrate (1) and comprising a matrix (2) of memory cells and an associated circuitry (3), the method comprising the following steps:

forming a plurality of gate electrodes (2a) of the memory cells projecting from the semiconductor substrate (1) in the matrix (2), the plurality of gate electrodes (2a) comprising a plurality of conductive layers (5, 7) and at least one conductive layer (7') in said circuitry (3);
forming conductive regions (9, 10) of the memory cells in the semiconductor substrate (1),
forming a filling dielectric layer (13) on the whole semiconductor substrate (1) until the plurality of gate electrodes (2a) of the cells and of the conductive layer (7') formed in the circuitry (3) are completely covered,
removing said conform filling dielectric layer (13) until upper portions (2b) of the plurality of gate electrodes (2a) of the cells are exposed and the conductive layer (7') formed in the circuitry (3) is completely exposed,
defining a plurality of gate electrodes (3a) of the transistors of the circuitry (3) in the conductive layer (7') formed in the circuitry (3),
forming source and drain regions of the transistors of the circuitry (3) in the semiconductor substrate (1).

The method also comprises the following steps:

forming spacers on the side walls of said plurality of gate electrodes (3a) of the transistors of said circuitry (3):
forming a silicide layer (17) on said plurality of electrodes (2a) of the memory cells, on said plurality of gate electrodes (3a) of the transistors of said circuitry (3) and on said conductive regions of the transistors of said circuitry (3);
forming a layer (18) of filling material on the whole of said semiconductor substrate (1) until said plurality of gate electrodes (3a) of the transistors of said circuitry (3) is completely covered and said plurality of matrix electrodes (2a) is completely covered;
defining contacts (19) for the conductive regions of said matrix (2) and of said circuitry (3) formed in a same step or in different steps.

Abstract translation: 一种用于制造集成在半导体衬底（1）上并包括存储器单元的矩阵（2）和相关电路（3）的非易失性存储器件的方法，所述方法包括以下步骤：形成多个栅电极 所述存储单元从所述矩阵（2）中的所述半导体衬底（1）突出，所述多个栅电极（2a）包括多个导电层（5,7）和所述电路中的至少一个导电层（7'） （3）; 在所述半导体衬底（1）中形成所述存储单元的导电区域（9,10），在所述半导体衬底（1）的整个半导体衬底（1）上形成填充介电层（13），直到所述单元的多个栅电极（2a） 形成在电路（3）中的导电层（7'）被完全覆盖，去除所述顺应填充介电层（13），直到电池的多个栅电极（2a）的上部（2b）被暴露并且导电 形成在电路（3）中的层（7'）完全暴露，限定电路（3）中形成在电路（3）中的导电层（7'）中的电路（3）的晶体管的多个栅电极（3a） 形成半导体衬底（1）中的电路（3）的晶体管的源极和漏极区域。 该方法还包括以下步骤：在所述电路（3）的晶体管的所述多个栅电极（3a）的侧壁上形成间隔物：在所述电路的所述多个电极（2a）上形成硅化物层（17） 在所述电路（3）的晶体管的所述多个栅电极（3a）上和所述电路（3）的晶体管的所述导电区上的存储单元; 在整个所述半导体衬底（1）上形成填充材料层（18），直到所述电路（3）的晶体管的多个栅电极（3a）被完全覆盖，并且所述多个矩阵电极（2a）是 完全覆盖 为相同步骤或不同步骤形成的所述矩阵（2）和所述电路（3）的导电区域定义触点（19）。