公开(公告)号：EP1804289A3

公开(公告)日：2008-10-22

申请号：EP06026787.9

申请日：2006-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Capetti, Gianfranco ,  Cantú, Pietro

IPC: H01L21/8247 ,  H01L27/115 ,  G03F1/14 ,  H01L21/768

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521

Abstract: A non volatile memory device is described being integrated on semiconductor substrate (11, 110) and comprising a matrix of non volatile memory cells (12, 120) organised in rows, called word lines, and columns, called bit lines, the device comprising:
- a plurality of active areas (13, 130) formed on the semiconductor substrate (11, 110) comprising a first and a second group (G1, G2; G3, G4) of active areas,
- the non volatile memory cells (12, 120) being integrated in the first group (G1, G3) of active areas, each non volatile memory cell (12, 120) comprising a source region, a drain region and a floating gate electrode coupled to a control gate electrode, at least one group (14, 140) of the memory cells (12, 120) sharing a common source region (15, 150) integrated on the semiconductor substrate (11, 110), the device being characterised in that:

- said plurality of active areas (13, 130) are equidistant from each other,
- a contact region (16, 160) is integrated in the second group (G2, G4) of active areas (13, 130) and is provided with at least one common source contact (17, 170) of said common source region (15, 150).

公开(公告)号：EP1675180A1

公开(公告)日：2006-06-28

申请号：EP04425936.4

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Brazzelli, Daniela

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate (50), of isolation regions (57) filled by field oxide (65) and of memory cells (500) separated each other by said isolation regions (57). The memory cells (500) include an electrically active region (51) surmounted by a gate electrode (52) electrically isolated from the semiconductor material substrate (50) by a first dielectric layer (53); the gate electrode (52) includes a floating gate (54) defined simultaneously to the active electrically region (51). A formation phase of said floating gate (54) exhibiting a substantially saddle shape including a concavity is proposed.

Abstract translation: 一种制造非易失性MOS半导体存储器件的方法包括：在半导体材料衬底（50）中由场氧化物（65）填充的隔离区（57）和彼此分离的存储单元（500）的形成阶段 所述隔离区（57）。 存储器单元（500）包括由第一介电层（53）与半导体材料衬底（50）电隔离的栅电极（52）覆盖的电有源区（51）; 栅电极（52）包括同时限定到有源电区域（51）的浮栅（54）。 提出了呈现包括凹面的基本鞍形的所述浮动闸门（54）的形成阶段。

公开(公告)号：EP1045440A1

公开(公告)日：2000-10-18

申请号：EP99830211.1

申请日：1999-04-14

Applicant: STMicroelectronics S.r.l.

Inventor： Bez, Roberto ,  Riva, Caterina ,  Servalli, Giorgio

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521

Abstract: Process for the manufacture of a non volatile memory with memory cells arranged in lines (2) and columns (3) in a matrix structure, with source lines (10) extending parallelly and intercalate to said lines (1), said source lines (10) formed by active regions intercalated to field oxide zones (4), said process comprising steps for the definition of active areas of said columns (3) of said matrix of non volatile memory cells and the definition of said field oxide zones (4), subsequent steps for the definition of the lines (2) of said matrix of non volatile memory cells, a following step for the definition of said source lines (10). In said step for the definition of the source lines a process step comprising a selective introduction of dopant is foreseen so to form a layer of buried silicon with high concentration of dopant (30), said layer of buried silicon (30) being formed to such a depth to coincide with the regions of silicon the underlying field oxide zones (4), a following introduction of dopant in said active regions of the source lines (10) to superficially contact said layer of buried silicon (30).

Abstract translation: 用于制造具有以矩阵结构的线（2）和列（3）排列的存储单元的非易失性存储器的方法，源极线（10）平行并插入所述线（1），所述源极线（10） ）由所述有源区插入到场氧化物区（4）中形成，所述方法包括用于定义所述非易失性存储单元矩阵的所述列（3）的有效面积和所述场氧化物区（4）的定义的步骤， 用于定义非易失性存储器单元的所述矩阵的行（2）的后续步骤，用于定义所述源极线（10）的后续步骤。 在用于定义源极线的所述步骤中，预期包括选择性引入掺杂剂的工艺步骤，以便形成具有高浓度掺杂剂（30）的掩埋硅层，所述掩埋硅层（30）形成为 深度与硅的区域与下面的场氧化物区域（4）重合，随后在源极线（10）的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层（30）。

公开(公告)号：EP1686620A1

公开(公告)日：2006-08-02

申请号：EP05425034.5

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Erbetta, Davide ,  Marangon, Maria Santina

IPC: H01L21/768 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: In a process for manufacturing a memory (2) having a plurality of memory cells (3) the steps of: forming a well (11), having a first type of conductivity, within a wafer (10) of semiconductor material; defining active regions (12) within the well (11) extending in a first direction (y); forming memory cells (3) within the active regions (12), each memory cell (3) having a source region (15) with a second type of conductivity, opposite to the first type of conductivity; and forming lines of electrical contact (20), which electrically contact source regions (15) aligned in a second direction (x). In the step of forming lines of electrical contact (20), the step of forming an electrical contact between the source regions (15) and portions (37) of the well (11) adjacent thereto in the second direction (x).

Abstract translation: 在用于制造具有存储器单元（3）的步骤的多个A存储器（2）的方法：形成阱（11），具有第一导电类型的半导体材料的晶片（10）内; 在第一方向（Y）延伸的孔（11）内 - 定义的有源区（12）; 有源区域内形成存储单元（3）（12），每个存储单元（3）具有与第二导电类型的，相反于第一导电类型的源极区（15）; 和在第二方向上排列的电接触件（20），该电接触源极区（15）的成型线（X）。 在形成电接触（20），在第二方向（x）的阱（11）与其相邻的源极区（15）和部分（37）之间的电接触形成的步骤的线的步骤。

公开(公告)号：EP1253635A1

公开(公告)日：2002-10-30

申请号：EP01830267.9

申请日：2001-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbara ,  Alessandri, Mauro ,  Servalli, Giorgio ,  Maurelli, Alfonso

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/66825

Abstract: The present invention relates to a method for sealing a nonvolatile memory device, characterized in that to comprise the following steps of: a) defining a nonvolatile memory cell (20), being composed by the overlap of a tunnel oxide (3), of a floating gate (1), of an interpoly dielectric (2), and of a control gate (4); b) deposing a silicon oxide layer (11) by a CVD (Chemical Vapor Deposition) at a temperature lower than 1000 °C on said control gate (4); c) densifing said silicon oxide layer (11) by a further thermal treatment (13). (Figure 5).

Abstract translation: 非易失性存储器件的密封方法技术领域本发明涉及一种用于密封非易失性存储器件的方法，其特征在于包括以下步骤：a）限定由隧道氧化物（3）的重叠构成的非易失性存储单元（20） 互补电介质（2）和控制栅极（4）的浮栅（1）; b）通过CVD（化学气相沉积）在所述控制栅极（4）上在低于1000℃的温度下沉积氧化硅层（11）; c）通过进一步的热处理（13）使所述氧化硅层（11）致密化。 （图5）。

公开(公告)号：EP1496548B1

公开(公告)日：2008-01-02

申请号：EP03425459.9

申请日：2003-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Baldi, Livio ,  Servalli, Giorgio

IPC: H01L21/762

CPC classification number: H01L21/76229

公开(公告)号：EP1677348A1

公开(公告)日：2006-07-05

申请号：EP05028380.3

申请日：2005-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pavan, Alessia ,  Servalli, Giorgio ,  Clementi, Gesare

IPC: H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: Method for manufacturing non volatile memory devices integrated on a semiconductor substrate (1) and comprising a matrix (2) of memory cells and an associated circuitry (3), the method comprising the following steps:

forming a plurality of gate electrodes (2a) of the memory cells projecting from the semiconductor substrate (1) in the matrix (2), the plurality of gate electrodes (2a) comprising a plurality of conductive layers (5, 7) and at least one conductive layer (7') in said circuitry (3);
forming conductive regions (9, 10) of the memory cells in the semiconductor substrate (1),
forming a filling dielectric layer (13) on the whole semiconductor substrate (1) until the plurality of gate electrodes (2a) of the cells and of the conductive layer (7') formed in the circuitry (3) are completely covered,
removing said conform filling dielectric layer (13) until upper portions (2b) of the plurality of gate electrodes (2a) of the cells are exposed and the conductive layer (7') formed in the circuitry (3) is completely exposed,
defining a plurality of gate electrodes (3a) of the transistors of the circuitry (3) in the conductive layer (7') formed in the circuitry (3),
forming source and drain regions of the transistors of the circuitry (3) in the semiconductor substrate (1).

The method also comprises the following steps:

forming spacers on the side walls of said plurality of gate electrodes (3a) of the transistors of said circuitry (3):
forming a silicide layer (17) on said plurality of electrodes (2a) of the memory cells, on said plurality of gate electrodes (3a) of the transistors of said circuitry (3) and on said conductive regions of the transistors of said circuitry (3);
forming a layer (18) of filling material on the whole of said semiconductor substrate (1) until said plurality of gate electrodes (3a) of the transistors of said circuitry (3) is completely covered and said plurality of matrix electrodes (2a) is completely covered;
defining contacts (19) for the conductive regions of said matrix (2) and of said circuitry (3) formed in a same step or in different steps.

Abstract translation: 一种用于制造集成在半导体衬底（1）上并包括存储器单元的矩阵（2）和相关电路（3）的非易失性存储器件的方法，所述方法包括以下步骤：形成多个栅电极 所述存储单元从所述矩阵（2）中的所述半导体衬底（1）突出，所述多个栅电极（2a）包括多个导电层（5,7）和所述电路中的至少一个导电层（7'） （3）; 在所述半导体衬底（1）中形成所述存储单元的导电区域（9,10），在所述半导体衬底（1）的整个半导体衬底（1）上形成填充介电层（13），直到所述单元的多个栅电极（2a） 形成在电路（3）中的导电层（7'）被完全覆盖，去除所述顺应填充介电层（13），直到电池的多个栅电极（2a）的上部（2b）被暴露并且导电 形成在电路（3）中的层（7'）完全暴露，限定电路（3）中形成在电路（3）中的导电层（7'）中的电路（3）的晶体管的多个栅电极（3a） 形成半导体衬底（1）中的电路（3）的晶体管的源极和漏极区域。 该方法还包括以下步骤：在所述电路（3）的晶体管的所述多个栅电极（3a）的侧壁上形成间隔物：在所述电路的所述多个电极（2a）上形成硅化物层（17） 在所述电路（3）的晶体管的所述多个栅电极（3a）上和所述电路（3）的晶体管的所述导电区上的存储单元; 在整个所述半导体衬底（1）上形成填充材料层（18），直到所述电路（3）的晶体管的多个栅电极（3a）被完全覆盖，并且所述多个矩阵电极（2a）是 完全覆盖 为相同步骤或不同步骤形成的所述矩阵（2）和所述电路（3）的导电区域定义触点（19）。

公开(公告)号：EP1675180B1

公开(公告)日：2009-12-09

申请号：EP04425936.4

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Brazzelli, Daniela

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

公开(公告)号：EP1786036A1

公开(公告)日：2007-05-16

申请号：EP05110648.2

申请日：2005-11-11

Applicant: STMicroelectronics S.r.l.

Inventor： Cremonesi, Carlo ,  Pavan, Alessia ,  Servalli, Giorgio

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, comprising the steps of: forming a gate dielectric ( 290 ) over a surface ( 210 ) of a semiconductor material layer ( 200 ); forming a conductive floating gate electrode ( 280 ) insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region ( 270 ) laterally to said floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode ( 260 ) of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning said floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, said lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the floating gate electrode; and etching the at least one isolation region essentially down to the gate dielectric, the protective layer protecting against etching a portion of the at least one isolation region near the gate dielectric.

Abstract translation: 一种用于制造包括浮置栅极MOS晶体管的非易失性存储单元的方法，包括以下步骤：在半导体材料层（200）的表面（210）上形成栅极电介质（290）; 形成通过栅极电介质与半导体材料层绝缘的导电浮栅电极（280）; 与所述浮栅电极横向形成至少一个隔离区域（270）; 挖掘所述至少一个隔离区域; 用导电材料填充挖掘的隔离区; 以及在所述浮置栅极上绝缘地形成所述浮置栅极MOS晶体管的导电控制栅极（260），其中形成所述浮置栅电极的步骤包括：将所述浮置栅电极横向对准所述至少一个隔离区域; 并且挖掘步骤包括：降低浮栅电极暴露表面下方的隔离区暴露表面，所述浮栅电极的所述降低暴露壁; 在浮栅电极的暴露壁上形成保护层; 并且将所述至少一个隔离区域基本上刻蚀到所述栅极电介质，所述保护层防止蚀刻栅极电介质附近的所述至少一个隔离区域的一部分。

公开(公告)号：EP1496548A1

公开(公告)日：2005-01-12

申请号：EP03425459.9

申请日：2003-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Baldi, Livio ,  Servalli, Giorgio

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

Abstract translation: 本发明涉及一种用于制造具有不同深度的隔离结构中单片集成半导体电子器件的方法。 本发明方法包括的定义上的半导体材料基板的有源区域的第一步骤中，形成在上述基片由真实伊辛沟槽隔离结构，然后与场氧化物，的限定光刻至少第一器件区域的第三步骤填充它们的第二步骤 ，并减少基板和所述第一器件区的场氧化物的垂直高度的第四步骤。