公开(公告)号：EP1143617A1

公开(公告)日：2001-10-10

申请号：EP00830249.9

申请日：2000-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Davide ,  Cleris, Mauro

IPC: H03K4/06

CPC classification number: H03K4/06 ,  H03K4/023

Abstract: An integrated circuit for producing a small slope voltage ramp (V OUT ) is constituted by a circuit generating a periodic triangular current signal (I GM1 ), a circuit generating, at the beginning of each period of the triangular signal, a pulse (V) of a certain duration (τ) much smaller than the period (T) of the triangular signal, a loop input at a node (B) with the triangular current signal and producing on the output node the desired slow voltage ramp (V OUT ).
The loop comprises a first hold circuit (C2, B UFFER2 ) coupled to the input node (B) by way of a first switch (SW2) controlled by the pulse (V), a transconductance operational amplifier (OTA1), whose inputs are respectively coupled to the input node (B) and to the output node (V OUT ), a second hold circuit (C1, B UFFER1 ) coupled to the output of the operational transconductance amplifier (OTA1) by way of a second switch (SW1) controlled in a complementary manner respect to the first switch (SW2), and a resistor (R) of a much smaller value than the ratio between the period (T) of the triangular signal and the capacitance of the storage capacitor (C2) of the first hold circuit, connected between the output of the second hold circuit and the input node (B).

Abstract translation: 用于产生小斜坡电压斜坡（VOUT）的集成电路由产生周期性三角形电流信号（IGM1）的电路构成，在三角波信号的每个周期的开始处产生电路的脉冲（V） 在三角形信号的周期（T）小的特定持续时间（τ），在三角形电流信号的节点（B）输入的环路，并在输出节点产生所需的慢电压斜坡（VOUT）。 环路包括通过由脉冲（V）控制的第一开关（SW2）耦合到输入节点（B）的第一保持电路（C2，BUFFER2），跨导运算放大器（OTA1），其输入端分别耦合 到输入节点（B）和输出节点（VOUT），第二保持电路（C1，BUFFER1）通过第二开关（SW1）耦合到工作跨导放大器（OTA1）的输出端，控制互补 （SW2）的方式和比三角形信号的周期（T）和第一保持电路的存储电容器（C2）的电容之间的比值小得多的电阻器（R） 连接在第二保持电路的输出和输入节点（B）之间。

公开(公告)号：EP1184672A1

公开(公告)日：2002-03-06

申请号：EP00830596.3

申请日：2000-09-01

Applicant: STMicroelectronics S.r.l.

Inventor： Botti, Edoardo ,  Cleris, Mauro ,  Grosso, Antonio

IPC: G01R23/20

CPC classification number: G01R23/20

Abstract: The present invention relates to an adjustable harmonic distortion detector comprising a clock signal source (9), means for the detection of a first period of evaluation (T1) and means for the detection of a second period of evaluation (T2). Said detector has the characteristic that a first block (12) memorizes a number equal to the clock pulses present in said first period of evaluation (T1), a multiplier block (16) makes a multiplication between said number stored in said first block (T1) and a multiplicative factor during said second period of evaluation (T2), a second block (23) memorizes the outcome, said second block (23) adapted to generate an output signal (27) when said outcome in said second block (23) is equal to zero.

Abstract translation: 本发明涉及在可调节的谐波失真检测器，包括一个时钟信号源（9）用于将所述检测的评估（T1）和手段用于检测评估（T2）的第二时间段的第一时间段的。 所述检测器具有的特性做了第一块（12）记忆数量等于存在于所述第一评价（T1）的周期的时钟脉冲，乘法器块（16），使间存储在所述第一块所述号码的乘法（T1 ）并且在评价（T2）的所述第二周期），第二块（23的乘法因子记忆的结果，所述第二块（23）angepasst在输出信号产生（27），当所述结果在所述第二块（23） 等于零。

公开(公告)号：EP1143617B1

公开(公告)日：2008-06-04

申请号：EP00830249.9

申请日：2000-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Davide ,  Cleris, Mauro

IPC: H03K4/06

CPC classification number: H03K4/06 ,  H03K4/023

公开(公告)号：EP1164695A1

公开(公告)日：2001-12-19

申请号：EP00830419.8

申请日：2000-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Davide ,  Nebuloni, Daniela ,  Cleris, Mauro

IPC: H03F1/34 ,  H03F1/32

CPC classification number: H03F1/3217 ,  H03F1/34

Abstract: The amplifier (1, 2) has an input (2a); an output (2c) supplying an output signal (Vo), and a feedback network (5) connected between the input (2a) and the output (2c), and a distortion detection circuit (1). The feedback network (5; 55) includes a first and a second feedback element (6, 7) arranged in series and forming an intermediate node (10) supplying an intermediate signal (VB) in phase with the output signal (Vo) in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit (1) includes a phase-comparating circuit (12, 15) which detects the phase of the output signal (Vo) and of the intermediate signal (VB), and generates a distortion-indicative signal (VCD), when the intermediate signal (VB) is in phase opposition with respect to the output signal (Vo).

Abstract translation: 放大器（1,2）具有在输入端（2a）的; 到输出（2C）提供给连接在所述输入端（2a）的间输出信号（VO），和一个反馈网络（5）和输出（2C），和一失真检测电路（1）。 反馈网络（5; 55）包括第一和第二反馈元件（6,7）串联布置并且在中间节点（10）形成在相供给到中间信号（VB）与在不存在的输出信号（VO） 失真的，并且在相反对与失真的存在的输出信号。 失真检测电路（1）包括相comparating电路（12，15），其检测所述输出信号（VO）的相位和中间信号的（VB），及基因率失真指示信号（VCD），当 中间信号（VB）是在相对于所述输出信号（VO）反相。

公开(公告)号：EP1164695B1

公开(公告)日：2006-09-06

申请号：EP00830419.8

申请日：2000-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Brambilla, Davide ,  Nebuloni, Daniela ,  Cleris, Mauro

IPC: H03F1/34 ,  H03F1/32

CPC classification number: H03F1/3217 ,  H03F1/34

公开(公告)号：EP1184672B1

公开(公告)日：2006-03-29

申请号：EP00830596.3

申请日：2000-09-01

Applicant: STMicroelectronics S.r.l.

Inventor： Botti, Edoardo ,  Cleris, Mauro ,  Grosso, Antonio

IPC: G01R23/20

CPC classification number: G01R23/20