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    PWM power amplifier with digital input
    1.
    发明公开
    PWM power amplifier with digital input 有权
    PWMLeistungsverstärkermit digitalem Eingang

    公开(公告)号：EP1028524A1

    公开(公告)日：2000-08-16

    申请号：EP99830073.5

    申请日：1999-02-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Botti, Edoardo ,  Grosso, Antonio

    IPC: H03F3/217 ,  H03M1/68 ,  H03M1/82

    CPC classification number: H03M1/68 ,  H03F3/217 ,  H03F2200/331 ,  H03M1/825

    Abstract: A digital input PWM power amplifier comprises:

    an oversampling and noise shaping circuit receiving pulse code modulated (PCM) digital input data organized in words of a first number M of bits at a certain bit rate (Fin) and outputting pulse code modulated digital data organized in words of a smaller number N of bits at a multiple bit rate (Fin∗K);
    a first bus transmitting a first number (P) of most significant bits (MSB) of said N bit words output from said first circuit and a second bus transmitting a second number (S) of least significant bits of said N bit words output from said first circuit;
    first and second PCM/PWM converters, respectively fed with said first and second number of bits transmitted through said first and said second bus, each converter including a counter driven by a clock signal (Fclock) of frequency equal to the product of the bit rate (Fin∗K) of the MSB and LSB bits transmitted on the respective bus and the square of the respective number of bits (P, S) generating reference digital words composed of said respective number of bits (P, S), defining ramps of digital values with a frequency identical to said multiple bit rate (Fin∗K), and a digital comparator receiving through a first input said reference digital words and through a second input the respective first and second number of bits (MSB, LSB) and outputting a respective PWM signal (MSBdig, LSBdig);
    the PWM signal (MSBig) output by said first converter, being summed to the so attenuated PWM signal (LSBdig) output by said second converter on the inverting input node (-) of said output power stage.

    Abstract translation: 数字输入PWM功率放大器包括：过采样和噪声整形电路，接收以一定比特率（Fin）的第一位数M字组织的脉码调制（PCM）数字输入数据，并输出脉冲编码调制数字数据组织 以多位比特率（Fin * K）的较小数目的N个字的字; 发送从所述第一电路输出的所述N位字的最高有效位（MSB）的第一数量（P）和从所述第一总线发送的所述N位字的第二数量（S）的最低有效位的第二总线的第一总线， 第一回路 第一和第二PCM / PWM转换器，分别馈送通过所述第一和所述第二总线传输的所述第一和第二位数，每个转换器包括由频率等于比特率乘积的时钟信号（Fclock）驱动的计数器 （P，S）的相应位数（P，S）的平方，生成由所述各个比特数（P，S）组成的参考数字字的平方根（Fin * K）和在相应总线上发送的LSB位， 具有与所述多位速率（Fin * K）相同频率的数字值，以及数字比较器，通过第一输入接收所述参考数字字，并通过第二输入接收相应的第一和第二位数（MSB，LSB）并输出 相应的PWM信号（MSBdig，LSBdig）; 由所述第一转换器输出的PWM信号（MSBig）与由所述第二转换器在所述输出功率级的反相输入节点（ - ）上输出的衰减的PWM信号（LSBdig）相加。

    Adjustable harmonic distortion detector, and method using same detector
    2.
    发明公开
    Adjustable harmonic distortion detector, and method using same detector 有权
    可调谐波失真探测器和程序，该探测器的帮助

    公开(公告)号：EP1184672A1

    公开(公告)日：2002-03-06

    申请号：EP00830596.3

    申请日：2000-09-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Botti, Edoardo ,  Cleris, Mauro ,  Grosso, Antonio

    IPC: G01R23/20

    CPC classification number: G01R23/20

    Abstract: The present invention relates to an adjustable harmonic distortion detector comprising a clock signal source (9), means for the detection of a first period of evaluation (T1) and means for the detection of a second period of evaluation (T2). Said detector has the characteristic that a first block (12) memorizes a number equal to the clock pulses present in said first period of evaluation (T1), a multiplier block (16) makes a multiplication between said number stored in said first block (T1) and a multiplicative factor during said second period of evaluation (T2), a second block (23) memorizes the outcome, said second block (23) adapted to generate an output signal (27) when said outcome in said second block (23) is equal to zero.

    Abstract translation: 本发明涉及在可调节的谐波失真检测器，包括一个时钟信号源（9）用于将所述检测的评估（T1）和手段用于检测评估（T2）的第二时间段的第一时间段的。 所述检测器具有的特性做了第一块（12）记忆数量等于存在于所述第一评价（T1）的周期的时钟脉冲，乘法器块（16），使间存储在所述第一块所述号码的乘法（T1 ）并且在评价（T2）的所述第二周期），第二块（23的乘法因子记忆的结果，所述第二块（23）angepasst在输出信号产生（27），当所述结果在所述第二块（23） 等于零。

    Power amplification equipment
    4.
    发明公开
    Power amplification equipment 有权
    功率放大设备

    公开(公告)号：EP1184973A1

    公开(公告)日：2002-03-06

    申请号：EP00830589.8

    申请日：2000-08-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Botti, Edoardo ,  Grosso, Antonio

    IPC: H03F3/217 ,  H03F1/30

    CPC classification number: H03F3/45475 ,  H03F1/305 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/45512

    Abstract: A power amplification apparatus receiving in input an enable signal (En) and an input square wave signal (C) is described. The apparatus comprises a device (6) receiving the input square wave signal (C) and the enable signal (En) and which produces a new enable signal (Ens) of the apparatus which is synchronized with a rise or down front of the input square wave signal (C), so that an output square wave signal (Vo) of the apparatus, which is normally shifted of a certain period fraction with respect to the square wave signal (C) in input to the apparatus, has the first (Ti) and the last (Tf) pulses which have a duration equal to a period fraction of the output square wave signal (Vo).

    Abstract translation: 描述了在输入端接收使能信号（En）和输入方波信号（C）的功率放大装置。 该设备包括接收输入方波信号（C）和使能信号（En）并且产生与输入平方的上升或下降同步的装置的新的使能信号（Ens）的装置（6） （C），使得相对于输入到装置中的方波信号（C）正常偏移一定周期分数的装置的输出方波信号（Vo）具有第一（Ti ）和持续时间等于输出方波信号（Vo）的周期分数的最后（Tf）脉冲。

    PWM bridge amplifier with input network configurable for analog or digital input not needing a triangular wave generator
    5.
    发明公开
    PWM bridge amplifier with input network configurable for analog or digital input not needing a triangular wave generator 有权
    脉宽调制桥式放大器具有可配置输入网络为模拟或数字输入不使用三角波发生器

    公开(公告)号：EP1001526A1

    公开(公告)日：2000-05-17

    申请号：EP98830685.8

    申请日：1998-11-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Botti, Edoardo ,  Grosso, Antonio ,  Masini, Marco

    IPC: H03F3/217

    CPC classification number: H03F3/2173

    Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output, comprises two identical amplifying modules (1, 2), one (1) for the amplifying channel relative to the direct or positive PWM output (Vo-If+) and the other (2) for the amplifying channel relative to the inverted or negative PWM output (Vo-If+). Each modules includes a switching output operational amplifier (O1), having a voltage mode noninverting input (In+), a current mode inverting input (In-) and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform, a logic inverter or a cascade of logic inverters (C1) coupled in cascade to the output of the integrator (O1, LOOP FILTER) and outputting a logic PWM signal, an output power stage (P1) converting the logic PWM signal output by said inverter or cascade of logic inverters (C1) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor (Rf) connecting the output of power stage (P1) to the inverting input (In-) of said operational amplifier (O1).

    Abstract translation: 具有在输入网络配置为标准PWM数字输入信号，相移PWM数字输入信号或模拟输入信号，并为标准PWM输出或相移PWM输出，A低频PWM输出桥式放大器包括两个相同的放大模块（1,2） 中，一个（1）用于相对于所述直接或正PWM输出端（Vo-如果+）和放大通道的另一个（2），用于相对于所述倒置的或负的PWM输出端（Vo-如果+）放大通道。 每个模块包括一个开关输出的运算放大器（01），具有电压模式的同相输入端（IN +），电流模式反相输入端（IN）和一个环路滤波器实现一个单个或多个斜率积分器输出廷的大致三角形的波形的信号 ，逻辑反相器或级联耦合到积分器的输出逻辑反相器（C1）（O1，环路滤波器）和输出廷逻辑PWM信号，以输出功率级（P1）由所述逻辑PWM信号输出转换的级联 逆变器或在PWM信号逻辑的级联，所述电路的两个电源轨的电势之间切换，和反馈电阻的反相器（C1）（RF）功率级（P1）的输出连接到反相输入端（IN- ）所述运算放大器的（O1）。

    Enhancement of the dynamic range of a multibit digital-to-analog converter
    9.
    发明公开
    Enhancement of the dynamic range of a multibit digital-to-analog converter 有权
    Dynamikbereichsverbesserung eines Multibit-Analog-Digital-Wandlers

    公开(公告)号：EP1691487A1

    公开(公告)日：2006-08-16

    申请号：EP05425062.6

    申请日：2005-02-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Grosso, Antonio ,  Meroni, Cristiano ,  Botti, Edoardo

    IPC: H03M1/18

    CPC classification number: H03M1/70

    Abstract: The dynamic range of operation of a digital-to-analog converter of an audio system, including at least first and second subsets of individually selectable elementary current sources for delivering analog output current contributions, a code conversion circuit for selecting elementary current sources of said subsets first and second in function of the value of each sampled code of a pulse code modulated input signal, is embedded by multiplying by a certain factor incoming digital codes of said pulse code modulated input signal after their value has remained lower than a predefined threshold value for a certain period of time and for as long as their value equals or surpasses than said threshold value and correspondingly scaling and de-scaling by the same factor the amplitude of said analog output current contributions produced by the elementary current sources of said two subsets.

    Abstract translation: 音频系统的数模转换器的动态动态范围，包括用于传送模拟输出电流贡献的单独可选择的基本电流源的至少第一和第二子集;代码转换电路，用于选择所述子集的基本电流源 在脉冲编码调制输入信号的每个采样码的值的函数中的第一和第二功能通过将所述脉冲编码调制输入信号的输入数字代码的值固定低于预定义的阈值 只要它们的值等于或超过所述阈值，并且通过相同的因子相应地缩放和缩小由所述两个子集的基本电流源产生的所述模拟输出电流贡献的幅度。

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