公开(公告)号：EP1376683A1

公开(公告)日：2004-01-02

申请号：EP02425428.6

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ciovacco, Francesco ,  Savardi, Chiara ,  Colombo, Roberto

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

Abstract: A process for forming trenches with an oblique profile and rounded top corners, including the steps of: in a semiconductor wafer (20), through a first polymerizing etch, forming depressions (28) delimited by rounded top corners (29); and through a second polymerizing etch, opening trenches (31) at the depressions (29). The second polymerizing etch is made in variable plasma conditions, so that the trenches (31) have oblique walls (37) with a constant slope (α).

Abstract translation: 用于形成具有倾斜轮廓和圆形顶角的沟槽的方法，包括以下步骤：在半导体晶片（20）中，通过第一聚合蚀刻，形成由圆形顶角（29）限定的凹陷（28）; 并且通过第二聚合蚀刻，在凹陷处（29）处打开沟槽（31）。 在可变等离子体条件下进行第二聚合蚀刻，使得沟槽（31）具有具有恒定斜率（α）的斜壁（37）。

公开(公告)号：EP1804281A1

公开(公告)日：2007-07-04

申请号：EP05425930.4

申请日：2005-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Roberto

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/30655 ,  H01L21/76281 ,  H01L21/76283

Abstract: A process for digging deep trenches in a body of semiconductor material envisages: forming a mask (3) having at least one opening (5), above a surface (2a) of a semiconductor body (2); forming a passivating layer (6, 6') conformally on the mask (3) and on the semiconductor body (2) within the opening (5); executing a directional etch so as to first remove the passivating layer (6, 6') at least from on top of the semiconductor body (2) and then etch the semiconductor body (2) through the opening (5). The steps of forming a passivating layer (6, 6') and executing a directional etch are carried out repeatedly in sequence so as to form a trench (10) through the opening (5). In a step of the process, moreover, a tapered portion (10") of the trench (10) is formed, which has a transverse dimension (W") decreasing as a distance (D) from the surface (2a) of the semiconductor body (2) increases.

Abstract translation: 一种用于在半导体材料的主体挖掘深沟槽方法设想：形成掩模（3），其具有半导体主体（2）中的至少一个开口（5），上述的表面（2A）; 形成钝化层（6，6“）共形地在掩模（3）和在所述半导体主体（2）的开口（5）内; 执行定向刻蚀以便首先从在半导体主体（2）的顶部去除负债至少婷层（6，6“），然后通过所述开口（5）蚀刻半导体主体（2）。 形成钝化层婷（6，6“）和执行定向蚀刻的步骤被顺序重复进行，以便形成通过所述开口（5）的沟槽（10）。 在该方法的一个步骤，更上方，锥形部分（10“）的沟槽（10）的形成，其具有横向尺寸（W”半导体的）降低从所述表面（2A）的距离（D） 体（2）增加。

公开(公告)号：EP1361603A3

公开(公告)日：2004-04-14

申请号：EP03009600.2

申请日：2003-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Ciovacco, Francesco ,  Colombo, Roberto ,  Savardi, Chiara

IPC: H01L21/3065 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of: depositing an auxiliary layer (30) on a substrate (20); depositing a layer (40) of screening material on the auxiliary layer (30); selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).

公开(公告)号：EP1376683B1

公开(公告)日：2007-03-07

申请号：EP02425428.6

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ciovacco, Francesco ,  Savardi, Chiara ,  Colombo, Roberto

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

公开(公告)号：EP1361603A2

公开(公告)日：2003-11-12

申请号：EP03009600.2

申请日：2003-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Ciovacco, Francesco ,  Colombo, Roberto ,  Savardi, Chiara

IPC: H01L21/3065

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of:

depositing an auxiliary layer (30) on a substrate (20);
depositing a layer (40) of screening material on the auxiliary layer (30);
selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and
removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).

Abstract translation: 一种用于制造半导体集成电子电路（CI）包括以下步骤的方法：在一个基板的辅助层（30）（20）上沉积; 该辅助层上沉积屏蔽材料的层（40）（30）; 选择性地去除屏蔽材料的层（40），以提供在屏蔽材料的层（40）的第一开口（41）和暴露于（30）的辅助层的区域; 和除去所述辅助层（30）的该区域，以形成在辅助层（30），其横截面朝着基板（20）变窄在（20）的基板的区域，以露出的第二开口（31）小 比由所述第一开口（41）的曝光区域。