公开(公告)号：EP1361603A3

公开(公告)日：2004-04-14

申请号：EP03009600.2

申请日：2003-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Ciovacco, Francesco ,  Colombo, Roberto ,  Savardi, Chiara

IPC: H01L21/3065 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of: depositing an auxiliary layer (30) on a substrate (20); depositing a layer (40) of screening material on the auxiliary layer (30); selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).

公开(公告)号：EP1376683B1

公开(公告)日：2007-03-07

申请号：EP02425428.6

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ciovacco, Francesco ,  Savardi, Chiara ,  Colombo, Roberto

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

公开(公告)号：EP1361603A2

公开(公告)日：2003-11-12

申请号：EP03009600.2

申请日：2003-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Ciovacco, Francesco ,  Colombo, Roberto ,  Savardi, Chiara

IPC: H01L21/3065

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of:

depositing an auxiliary layer (30) on a substrate (20);
depositing a layer (40) of screening material on the auxiliary layer (30);
selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and
removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).

Abstract translation: 一种用于制造半导体集成电子电路（CI）包括以下步骤的方法：在一个基板的辅助层（30）（20）上沉积; 该辅助层上沉积屏蔽材料的层（40）（30）; 选择性地去除屏蔽材料的层（40），以提供在屏蔽材料的层（40）的第一开口（41）和暴露于（30）的辅助层的区域; 和除去所述辅助层（30）的该区域，以形成在辅助层（30），其横截面朝着基板（20）变窄在（20）的基板的区域，以露出的第二开口（31）小 比由所述第一开口（41）的曝光区域。

公开(公告)号：EP1394835A1

公开(公告)日：2004-03-03

申请号：EP02425536.6

申请日：2002-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Ciovacco, Francesco ,  Somboli, Fabio ,  Fazio, Giuseppe ,  Alba, Simone

IPC: H01J37/32

CPC classification number: H01J37/3244

Abstract: A method (300) and a corresponding apparatus for detecting a leak of external air into a plasma reactor are proposed. The method of the invention includes the steps of: establishing (340) a plasma inside the reactor, the plasma having a composition suitable to generate at least one predetermined compound when reacting with the air, detecting (345) a light emission of the plasma, and analyzing (350-375) the light emission to identify the presence of the at least one predetermined compound.

Abstract translation: 的方法（300），以及用于检测外部空气的漏入等离子体反应器中的相应设备的提议。 本发明的方法包括以下步骤：建立（340）一个反应器内的等离子体中，具有适合于产生至少一个预定的化合物当与空气反应生成的组合物的等离子体，检测（345）的等离子体的发光， 和分析（350-375）的光发射以识别至少一个预定的化合物的存在。

公开(公告)号：EP1376683A1

公开(公告)日：2004-01-02

申请号：EP02425428.6

申请日：2002-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ciovacco, Francesco ,  Savardi, Chiara ,  Colombo, Roberto

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

Abstract: A process for forming trenches with an oblique profile and rounded top corners, including the steps of: in a semiconductor wafer (20), through a first polymerizing etch, forming depressions (28) delimited by rounded top corners (29); and through a second polymerizing etch, opening trenches (31) at the depressions (29). The second polymerizing etch is made in variable plasma conditions, so that the trenches (31) have oblique walls (37) with a constant slope (α).

Abstract translation: 用于形成具有倾斜轮廓和圆形顶角的沟槽的方法，包括以下步骤：在半导体晶片（20）中，通过第一聚合蚀刻，形成由圆形顶角（29）限定的凹陷（28）; 并且通过第二聚合蚀刻，在凹陷处（29）处打开沟槽（31）。 在可变等离子体条件下进行第二聚合蚀刻，使得沟槽（31）具有具有恒定斜率（α）的斜壁（37）。