公开(公告)号：EP1168602A1

公开(公告)日：2002-01-02

申请号：EP00830439.6

申请日：2000-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Colonna, Vittorio ,  Baschirotto, Andrea ,  Cusinato, Paolo ,  Gandolfi, Gabriele

IPC: H03F3/45

CPC classification number: H03F3/45192 ,  H03F2203/45682

Abstract: The present invention refers to a completely differential operational amplifier of the folded cascode type.
In one embodiment the completely differential operational amplifier of the folded cascode type comprises: a differential output stage (15, 16, 17, 18, 19, 20 21, 22); a differential input stage (11, 12) able to drive said output stage (15, 16, 17, 18, 19, 20 21, 22); said differential output stage (15, 16, 17, 18, 19, 20 21, 22) includes a first branch (15, 16, 17, 18) having at least a first (16) and a second (17) transistor, and a second branch (19, 20 21, 22) having at least a third (20) and a fourth (21) transistor; said first (15, 16, 17, 18) and second (19, 20 21, 22) branch are coupled to a first (VDD) and to a second (GND) feeding voltage; a feedback circuit (40) of said first (16), second (17), third (20) and fourth (21) transistors; characterized in that said feedback circuit (40) is constituted by a single amplifier (40) having four inputs (IN1, IN2, IN3, IN4) and four outputs (OUT1, OUT2, OUTS, OUT4), said four inputs (IN1, IN2, IN3, IN4) take the voltage present on a terminal (23, 13, 24, 14) of said first (16), second (17), third (20) and fourth (21) transistors, and said four outputs (OUT1, OUT2, OUT3, OUT4) provide each a voltage to the control elements of said first (16), second (17), third (20) and fourth (21) transistors, which depend on the value of the input voltage of said four inputs (IN1, IN2, IN3, IN4).

Abstract translation: 本发明涉及一种折叠共源共栅型完全差分运算放大器。 在一个实施例中，折叠共源共栅类型的完全差分运算放大器包括：差分输出级（15,16,17,18,19,20,21,22）;以及差分放大级 能够驱动所述输出级（15,16,17,18,19,20,21,22）的差动输入级（11,12）;以及能够驱动所述输出级 所述差分输出级（15,16,17,18,19,20,21,22）包括具有至少第一（16）和第二（17）晶体管的第一支路（15,16,17,18），以及 具有至少第三晶体管（20）和第四晶体管（21）的第二分支（19,20,21,22） 所述第一（15,16,17,18）和第二（19,20,21,22）分支耦合到第一（VDD）和第二（GND）馈电电压; 所述第一（16），第二（17），第三（20）和第四（21）晶体管的反馈电路（40） 其特征在于，所述反馈电路（40）由具有四个输入（IN1，IN2，IN3，IN4）和四个输出（OUT1，OUT2，OUTS，OUT4）的单个放大器（40）构成，所述四个输入（IN1，IN2 ，IN3，IN4）获得所述第一（16），第二（17），第三（20）和第四（21）晶体管的端子（23,13,24,14）上存在的电压，并且所述四个输出（OUT1 ，OUT2，OUT3，OUT4）向所述第一（16），第二（17），第三（20）和第四（21）晶体管的控制元件提供每个电压，这取决于所述四个 输入（IN1，IN2，IN3，IN4）。

公开(公告)号：EP1168602B1

公开(公告)日：2005-11-23

申请号：EP00830439.6

申请日：2000-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Colonna, Vittorio ,  Baschirotto, Andrea ,  Cusinato, Paolo ,  Gandolfi, Gabriele

IPC: H03F3/45

CPC classification number: H03F3/45192 ,  H03F2203/45682

公开(公告)号：EP1324497B1

公开(公告)日：2004-09-29

申请号：EP01830812.2

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Colonna, Vittorio ,  Baschirotto, Andrea

IPC: H03M3/00

CPC classification number: H03M3/382 ,  H03M3/406 ,  H03M3/458

公开(公告)号：EP1324498B1

公开(公告)日：2005-08-03

申请号：EP02012046.5

申请日：2002-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Baschirotto, Andrea ,  Colonna, Vittorio

IPC: H03M3/00

CPC classification number: H03M3/38 ,  H03M3/37 ,  H03M3/406

公开(公告)号：EP1324497A1

公开(公告)日：2003-07-02

申请号：EP01830812.2

申请日：2001-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Colonna, Vittorio ,  Baschirotto, Andrea

IPC: H03M3/00

CPC classification number: H03M3/382 ,  H03M3/406 ,  H03M3/458

Abstract: The present invention relates a method for self-calibrating a frequency of a modulator circuit, said sigma - delta modulator (40) having a go path (15) and a feedback path (19), said go path (15) realized by the series of a resonator circuit (31) and of an analog to digital conversion ADC block (18), said feedback (19) path being realized by a digital to conversion DAC block (19), the inventive method comprising the following succession of steps: a) to apply a pulse (20) in input (IN) to said resonator circuit (31); b) to measure the oscillating frequency of the output signal (4) from said resonator circuit (31) in response of said pulse (20) when the feedback path (19) of said sigma - delta modulator (40) is opened; c) to perform a comparison between said oscillating frequency of said resonator circuit (31) with a frequency (f 0 ) known a priori; d) to modify in a proportional way said oscillating frequency of said resonator circuit (31) in function of said comparison performed at the previous step (c). The inventive circuit has the characteristic that a resonator circuit (31) is composed by at least an integrator filter (16, 17) having on its feedback path a variable gain ("g") amplifier (21), said variable gain ("g") of said amplifier (21) being modified in a proportional way in function of a comparison between the output signal frequency from said resonator circuit (31) due to a pulse (20) response present to its input (IN) and a frequency (f 0 ) known a priori when said feedback path (19) is opened.

Abstract translation: 本发明涉及用于自校准的调制器电路的频率，所述Σ的方法 - 德尔塔调制器具有由串联实现一个去路径（15）和反馈路径（19），所述走路径（15）（40） 谐振器电路（31）和模拟到数字转换ADC块（18）组成，所述反馈（19）路径由一个数字转化DAC块（19），本发明的方法包括以下步骤以下相继实现：一个 ）施加脉冲（20）（在输入端（IN）连接到所述谐振器电路31）; b）至测量的输出信号（4）的振荡频率从所述谐振器电路（31）在当所述Σ的反馈路径（19），所述脉冲（20）的响应 - Δ调制器（40）被打开; c）与先验已知的一个频率（f 0）来执行所述谐振器电路（31）的所述摆动频率之间的比较; D）在成比例的方式修改所述在前面的步骤（c）中进行所述比较的函数，所述谐振器电路（31）的振荡频率。 本发明的电路已经特性没有谐振器电路（31）通过至少在具有其反馈通路上的可变增益（“G”）放大器（21）积分器的过滤器（16,17）组成，所述可变增益（“克 “）的所述放大器（21）被修改以成比例的方式在从所述谐振器电路（31）的输出信号的频率之间的比较的函数，由于其输入端（IN）和一个频率的脉冲（20），响应本（ f 0的）先验已知的，当所述反馈通路（19）被打开。

公开(公告)号：EP1172936A1

公开(公告)日：2002-01-16

申请号：EP00830485.9

申请日：2000-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Baschirotto, Andrea ,  Colonna, Vittorio ,  Cusinato, Paolo

IPC: H03M3/02

CPC classification number: H03M3/502 ,  H03M7/3022

Abstract: The present invention refers to a digital analogical converter comprising a sigma delta cascade modulator having two outputs, particularly a third order sigma delta modulator 2+1.
In an embodiment the digital analogical converter comprises: a sigma delta modulator (1) of the type having two outputs (67, 68) able to supply a first (Y1) and a second (Y2) signal to said two outputs (67, 68); a reconstruction circuit (2) of first said (Y1) and second (Y2) signal able to provide a reconstructed signal (Yout); a filter (3) able to filter said reconstructed signal (Yout); characterized in that said reconstruction circuit (2) combines said first (Y1) and second (Y2) signals according to the following relationship Yout= Y1* (1+ Z -1 ) - Y2* (1- Z -1 ) + Y2* Z -2 * (1- Z -1 )    where
Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

Abstract translation: 本发明涉及包括具有两个输出的Σ-Δ级联调制器的数字模拟转换器，特别是三阶Σ-Δ调制器2 + 1。 在一个实施例中，数字模拟转换器包括：具有两个能够向所述两个输出端（67,68）提供第一（Y1）和第二（Y2））信号的两个输出端（6,7,68）的Σ-Δ调制器（1） ）; 第一所述（Y1）和第二（Y2）信号的重建电路（2）能够提供重建信号（Yout）; 能够对所述重建信号（Yout）进行滤波的滤波器（3）; 其特征在于，所述重构电路（2）根据以下关系组合所述第一（Y1）和第二（Y2）信号：Yout = Y1 *（1+ Z -1） - Y2 *（1-Z < 其中Yout对应于所述重建信号，Y1对应于所述第一信号，Y2对应于所述根据信号的Z（Z-1>）+ Y2 * Z < 对应于Z变换。

公开(公告)号：EP1172936B1

公开(公告)日：2005-03-09

申请号：EP00830485.9

申请日：2000-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Baschirotto, Andrea ,  Colonna, Vittorio ,  Cusinato, Paolo

IPC: H03M3/02

CPC classification number: H03M3/502 ,  H03M7/3022

公开(公告)号：EP1458096A1

公开(公告)日：2004-09-15

申请号：EP03425120.7

申请日：2003-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Baschirotto, Andrea ,  Liguori, Pietro ,  Colonna, Vittorio ,  Gandolfi, Gabriele

IPC: H03H11/12 ,  H03H11/24

CPC classification number: H03H11/1291 ,  H03H7/24 ,  H03H11/24

Abstract: The present invention refers to a control system for the characteristic parameters of an active filter and to the relative method.
In one embodiment the control system for the characteristic parameters of an active filter (10) comprising: a system (20) for the determination of the technological distribution of the components that provides the information (Ein) related to said technological distribution of the components; an elaboration system (40) for said information (Ein) related to said technological distribution of the components; an active filter (10) including at least two programmable passive circuital elements (R1, R2, R3) receiving said information (Ein) related to said technological distribution of the components; said elaboration system (40), being aware of the topology for said active filter (10), comprises means for determining the value for said at least two programmable passive circuital elements (R1, R2, R3); means for correcting the value for said at least two programmable passive circuital elements (R1, R2, R3) according to the value of the information related to said technological distribution of the components; means for determining the programming values (E1, E2, E3) for said at least two programmable passive circuital elements (R1, R2, R3).

Abstract translation: 本发明涉及一种用于有源滤波器的特性参数的控制系统及其相关方法。 在一个实施例中，用于有源滤波器（10）的特性参数的控制系统包括：用于确定提供与所述技术分布相关的信息（Ein）的组件的技术分布的系统（20） 的组件; 用于与所述组件的所述技术分布相关的所述信息（Ein）的详细系统（40） 包括至少两个可编程无源电路元件（R1，R2，R3）的有源滤波器（10），其接收与所述组件的所述技术分布有关的所述信息（Ein）; 所述精细化系统（40）知道所述有源滤波器（10）的拓扑结构，包括用于确定所述至少两个可编程无源电路元件（R1，R2，R3）的值的装置; 用于根据与所述组件的所述技术分布有关的信息的值来校正所述至少两个可编程无源电路元件（R1，R2，R3）的值的装置; 用于确定所述至少两个可编程无源电路元件（R1，R2，R3）的编程值（E1，E2，E3）的装置。

公开(公告)号：EP1324498A1

公开(公告)日：2003-07-02

申请号：EP02012046.5

申请日：2002-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Gandolfi, Gabriele ,  Baschirotto, Andrea ,  Colonna, Vittorio

IPC: H03M3/00

CPC classification number: H03M3/38 ,  H03M3/37 ,  H03M3/406

Abstract: A method of self-calibrating a modulator comprising at least one integrator (23, 24) liable to incur a phase error is disclosed. Advantageously according to the invention, the calibration method comprises at least one step of reading a response to pulse of said modulator, a step of calculating a phase error parameter (b 1 , b 2 ) of the integrator, and a step of calibrating the phase error parameter (b 1 , b 2 ). In addition, the calibration step provides a count (N1) of response-to-pulse samples lying above suitable threshold values (y1), and a change in the value (Cv) of a capacitor associated with the integrator according to the sample count (N1).
Also disclosed is an integrator system with phase error correction, which comprises an integrator (17), having an input terminal (A) connected to an inverting output terminal (B) through a first feedback capacitor (C1), and a second input capacitor (C2) connected between a first input terminal (IN+) of the integrator system and the input terminal (A) of the integrator (17). Advantageously according to the invention, the integrator system further comprises a phase error correction portion (18) feedback connected between the output terminal (B) and the input terminal (A) of the integrator (17), the correction portion (18) having a variable capacitance value.

Abstract translation: 公开了一种自校准包括至少一个容易产生相位误差的积分器（23,24）的调制器的方法。 有利地，根据本发明，校准方法包括读取对所述调制器的脉冲的响应的至少一个步骤，计算积分器的相位误差参数（b1，b2）的步骤和校准相位误差参数的步骤 （b1，b2）。 此外，校准步骤提供位于合适的阈值（y1）之上的响应脉冲样本的计数（N1），以及根据样本计数与积分器相关联的电容器的值（Cv）的变化（ N1）。 还公开了一种具有相位误差校正的积分器系统，其包括积分器（17），其具有通过第一反馈电容器（C1）连接到反相输出端子（B）的输入端子（A）和第二输入电容器 C2）连接在积分器系统的第一输入端（IN +）和积分器（17）的输入端（A）之间。 有利地，根据本发明，积分器系统还包括连接在积分器（17）的输出端子（B）和输入端子（A）之间的相位误差校正部分（18），校正部分（18）具有 可变电容值。