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    Digital to analogue converter comprising a third order sigma delta modulator
    2.
    发明公开
    Digital to analogue converter comprising a third order sigma delta modulator 有权
    Digital-Analog-Wandler mit Sigma-Delta-Modulator dritter Ordnung

    公开(公告)号：EP1172936A1

    公开(公告)日：2002-01-16

    申请号：EP00830485.9

    申请日：2000-07-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gandolfi, Gabriele ,  Baschirotto, Andrea ,  Colonna, Vittorio ,  Cusinato, Paolo

    IPC: H03M3/02

    CPC classification number: H03M3/502 ,  H03M7/3022

    Abstract: The present invention refers to a digital analogical converter comprising a sigma delta cascade modulator having two outputs, particularly a third order sigma delta modulator 2+1.
    In an embodiment the digital analogical converter comprises: a sigma delta modulator (1) of the type having two outputs (67, 68) able to supply a first (Y1) and a second (Y2) signal to said two outputs (67, 68); a reconstruction circuit (2) of first said (Y1) and second (Y2) signal able to provide a reconstructed signal (Yout); a filter (3) able to filter said reconstructed signal (Yout); characterized in that said reconstruction circuit (2) combines said first (Y1) and second (Y2) signals according to the following relationship Yout= Y1* (1+ Z -1 ) - Y2* (1- Z -1 ) + Y2* Z -2 * (1- Z -1 )    where
    Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

    Abstract translation: 本发明涉及包括具有两个输出的Σ-Δ级联调制器的数字模拟转换器，特别是三阶Σ-Δ调制器2 + 1。 在一个实施例中，数字模拟转换器包括：具有两个能够向所述两个输出端（67,68）提供第一（Y1）和第二（Y2））信号的两个输出端（6,7,68）的Σ-Δ调制器（1） ）; 第一所述（Y1）和第二（Y2）信号的重建电路（2）能够提供重建信号（Yout）; 能够对所述重建信号（Yout）进行滤波的滤波器（3）; 其特征在于，所述重构电路（2）根据以下关系组合所述第一（Y1）和第二（Y2）信号：Yout = Y1 *（1+ Z -1） - Y2 *（1-Z < 其中Yout对应于所述重建信号，Y1对应于所述第一信号，Y2对应于所述根据信号的Z（Z-1>）+ Y2 * Z < 对应于Z变换。

    Switched-capacitor, fully-differential operational amplifier with high switching frequency
    3.
    发明公开
    Switched-capacitor, fully-differential operational amplifier with high switching frequency 审中-公开
    与开关电容器和高Schaltgefrequenz全差分运算放大器

    公开(公告)号：EP1168603A1

    公开(公告)日：2002-01-02

    申请号：EP00830449.5

    申请日：2000-06-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baschirotto, Andrea ,  Cusinato, Paolo

    IPC: H03F3/45

    CPC classification number: H03F3/45708 ,  H03F3/45183 ,  H03F2203/45461 ,  H03F2203/45511 ,  H03F2203/45594 ,  H03F2203/45666

    Abstract: Fully-differential, switched-capacitor circuit having a first and second input terminal (5a, 5b), and including: an operational amplifier (2, 41) having a first and a second differential input (4a, 4b), a first and a second output terminal (8a, 8b) and a bias control terminal (17); a feedback network (9a, 9b), connected between the differential outputs (8a, 8b) and the input terminals (5a, 5b), and having intermediate nodes connected to the differential inputs (4a, 4b) of the operational amplifier (2, 41); and a control circuit (3), including a detection network (19) and an error amplifier (20, 21). The error amplifier (20) has a first input receiving a desired common-mode voltage (V XID ), and an output connected to the bias control terminal (17) and supplying a control voltage (V XC ). The detection network (19) has a first and a second input connected directly, respectively, to the second input terminal (4a, 4b) of the operational amplifier (2, 41), and an output connected to a second input of the error amplifier (20), and supplying a common-mode drive voltage (V XCM ).

    Abstract translation: 全差分开关电容电路，其具有第一和第二输入端子（5A，5B），并且包括：一个运算放大器（2，41），具有第一和第二差分输入端（4A，4B），一个第一和一个 第二输出端子（8A，8B）和一个偏置控制端（17）; 反馈网络（9A，9B），连接在所述差分输出之间（8A，8B）和所述输入端子（5A，5B），并具有连接到所述差分输入中间节点（4A，4B）的运算放大器（2， 41）; 和控制电路（3），包括检测网络（19）和误差放大器（20，21）。 误差放大器（20）具有连接到偏置控制端子（17）的第一输入端接收期望的共模电压（VXID），并输出和提供控制电压（VXC）。 检测网络（19）具有第一和分别直接连接，一个第二输入端，所述第二输入端（4A，4B）的运算放大器（2，41），以及连接到所述误差放大器的第二输入输出 （20）和供给的共模电压驱动器（VXCM）。

    A method of improving the signal/noise ratio of a sigma-delta modulator and a circuit which uses the method
    4.
    发明公开
    A method of improving the signal/noise ratio of a sigma-delta modulator and a circuit which uses the method 有权
    一种用于改善的Σ/Δ调制器的信号/噪声比的方法，这个过程使用的电路

    公开(公告)号：EP1202461A1

    公开(公告)日：2002-05-02

    申请号：EP00830700.1

    申请日：2000-10-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cusinato, Paolo ,  Baschirotto, Andrea

    IPC: H03M3/04

    CPC classification number: H03M3/364 ,  H03M3/406 ,  H03M3/43 ,  H03M3/45 ,  H03M3/454

    Abstract: A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability which comprises the following steps: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also comprises the following steps: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

    Abstract translation: - 定义对应于该调制器的不稳定状态的比特序列，监测输出的比特由流：重新建立其稳定性的方法，包括以下步骤过程中改善的sigma-delta调制器的信号/噪声比的方法 调制器来检查是否含有不稳定的位序列，并且如果在输出中检测到不稳定性的位序列复位调制器到零。 到即使在检测和重新建立稳定性的确保调制器的高信/噪比，该方法因此包括以下步骤：延迟输出的比特流由调制器至少为检测到不稳定性的位所需要的时间 序列，并通过与预定的比特序列替换它修改在延迟期间内的输出位序列。

    Completely differential operational amplifier of the folded cascode type
    5.
    发明公开
    Completely differential operational amplifier of the folded cascode type 有权
    折叠共源共栅型完全差分运算放大器

    公开(公告)号：EP1168602A1

    公开(公告)日：2002-01-02

    申请号：EP00830439.6

    申请日：2000-06-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Colonna, Vittorio ,  Baschirotto, Andrea ,  Cusinato, Paolo ,  Gandolfi, Gabriele

    IPC: H03F3/45

    CPC classification number: H03F3/45192 ,  H03F2203/45682

    Abstract: The present invention refers to a completely differential operational amplifier of the folded cascode type.
    In one embodiment the completely differential operational amplifier of the folded cascode type comprises: a differential output stage (15, 16, 17, 18, 19, 20 21, 22); a differential input stage (11, 12) able to drive said output stage (15, 16, 17, 18, 19, 20 21, 22); said differential output stage (15, 16, 17, 18, 19, 20 21, 22) includes a first branch (15, 16, 17, 18) having at least a first (16) and a second (17) transistor, and a second branch (19, 20 21, 22) having at least a third (20) and a fourth (21) transistor; said first (15, 16, 17, 18) and second (19, 20 21, 22) branch are coupled to a first (VDD) and to a second (GND) feeding voltage; a feedback circuit (40) of said first (16), second (17), third (20) and fourth (21) transistors; characterized in that said feedback circuit (40) is constituted by a single amplifier (40) having four inputs (IN1, IN2, IN3, IN4) and four outputs (OUT1, OUT2, OUTS, OUT4), said four inputs (IN1, IN2, IN3, IN4) take the voltage present on a terminal (23, 13, 24, 14) of said first (16), second (17), third (20) and fourth (21) transistors, and said four outputs (OUT1, OUT2, OUT3, OUT4) provide each a voltage to the control elements of said first (16), second (17), third (20) and fourth (21) transistors, which depend on the value of the input voltage of said four inputs (IN1, IN2, IN3, IN4).

    Abstract translation: 本发明涉及一种折叠共源共栅型完全差分运算放大器。 在一个实施例中，折叠共源共栅类型的完全差分运算放大器包括：差分输出级（15,16,17,18,19,20,21,22）;以及差分放大级 能够驱动所述输出级（15,16,17,18,19,20,21,22）的差动输入级（11,12）;以及能够驱动所述输出级 所述差分输出级（15,16,17,18,19,20,21,22）包括具有至少第一（16）和第二（17）晶体管的第一支路（15,16,17,18），以及 具有至少第三晶体管（20）和第四晶体管（21）的第二分支（19,20,21,22） 所述第一（15,16,17,18）和第二（19,20,21,22）分支耦合到第一（VDD）和第二（GND）馈电电压; 所述第一（16），第二（17），第三（20）和第四（21）晶体管的反馈电路（40） 其特征在于，所述反馈电路（40）由具有四个输入（IN1，IN2，IN3，IN4）和四个输出（OUT1，OUT2，OUTS，OUT4）的单个放大器（40）构成，所述四个输入（IN1，IN2 ，IN3，IN4）获得所述第一（16），第二（17），第三（20）和第四（21）晶体管的端子（23,13,24,14）上存在的电压，并且所述四个输出（OUT1 ，OUT2，OUT3，OUT4）向所述第一（16），第二（17），第三（20）和第四（21）晶体管的控制元件提供每个电压，这取决于所述四个 输入（IN1，IN2，IN3，IN4）。

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