公开(公告)号：EP1816675A1

公开(公告)日：2007-08-08

申请号：EP06425059.0

申请日：2006-02-03

Applicant: STMicroelectronics S.r.l.

Inventor： Costantini, Sonia ,  Pavan, Alessia ,  Servalli, Giorgio

IPC: H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L27/11539 ,  H01L27/11543 ,  H01L27/11546

Abstract: Process for manufacturing a non volatile memory electronic device (2) integrated on a semiconductor substrate (1) which comprises a matrix of non volatile memory cells (4), said memory cells (4) organised in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors (3), comprising the steps of:
- forming, by means of a photo-lithographic process which provides the use of a first photo-lithographic mask, gate electrodes (12) of the high voltage transistors (3) projecting from a first portion (A) of the semiconductor substrate (1).
- forming first spacers (15) on the side walls of the gate electrodes (12) of said high voltage transistors (3) of a first length (L1),
- forming, by means of a photo-lithographic process which provides the use of a second photo lithographic mask which covers said high voltage transistors (3), gate electrodes (16) of said memory cells (4) projecting from a second portion (B) of said semiconductor substrate (1), each of said gate electrodes (16) of memory cells (4) comprising a floating gate electrode (FG) and a control gate electrode (CG)

Abstract translation: 一种集成在半导体衬底（1）上的非易失性存储器件（2）的制造方法，该半导体衬底（1）包括非易失性存储器单元（4）的矩阵，所述存储单元（4）被组织成行，称为字线和列， 所谓的位线和包括高压晶体管（3）的相关电路，包括以下步骤： - 通过提供使用第一光刻掩模的光刻工艺，形成所述第一光刻掩模的栅电极（12） 从半导体衬底（1）的第一部分（A）伸出的高电压晶体管（3）。 - 在第一长度（L1）的所述高压晶体管（3）的栅极（12）的侧壁上形成第一间隔物（15）， - 通过光刻工艺形成，所述光刻工艺提供使用 覆盖所述高压晶体管（3）的第二光刻掩模，从所述半导体衬底（1）的第二部分（B）突出的所述存储单元（4）的栅电极（16），每个所述栅电极 ）包括浮栅电极（FG）和控制栅电极（CG）的存储单元（4）