公开(公告)号：EP1104022A1

公开(公告)日：2001-05-30

申请号：EP99830742.5

申请日：1999-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbera ,  Peschiaroli, Daniela ,  Palumbo, Elisabetta ,  Zatelli, Nicola

IPC: H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

Abstract: The active areas and the body regions for the LV MOS transistors, for the HV MOS transistors and for the EPROM cells are formed on a silicon substrate, a layer of thermal oxide is formed, and a layer of polycrystalline silicon is formed on it, the last-mentioned layer is removed selectively to form the floating gate electrodes (13a) of the cells, the source and drain regions of the cells are formed, the silicon of the areas of the HV MOS transistors is exposed, a layer of HTO oxide is formed and nitrided, the silicon of the areas of the LV MOS transistors is exposed, a layer of thermal oxide (16) is formed on the exposed areas, a second layer of polycrystalline silicon is deposited and is then removed selectively to form the gate electrodes of the LV and HV MOS transistors (17c, 17b) and the control gate electrodes (17a) of the cells, and the source and drain regions of the LV and HV MOS transistors are formed. Owing to the simultaneous formation of the gate dielectric of the HV MOS transistors and the intermediate dielectric of the cells, and the use of a material (nitrided HTO oxide) which is impermeable to the oxygen atoms of the subsequent thermal oxidation, the number of the operations in the process is smaller than in the prior art process.

Abstract translation: 有源区和用于LV MOS晶体管的体区，用于HV MOS晶体管和用于EPROM细胞在一个硅衬底上形成时，热氧化物的层被形成，和多晶硅层形成在其上，所述 最后提到的层被选择性地移除以形成所述单元的浮置栅电极（13A），该单元的源区和漏区上形成时，HV MOS晶体管的区域中的硅被暴露，HTO氧化物层是 形成，并且氮化中，LV MOS晶体管的区域中的硅被暴露，热氧化层（16）形成在暴露区域，多晶硅的第二层被沉积，然后除去有选择地形成栅电极 LV和HV MOS晶体管（17C，17B）和所述单元的控制栅电极（17A），和LV和HV MOS晶体管的源区和漏区的形成。 由于HV MOS晶体管的栅极电介质和细胞的中间电介质，以及使用的材料（氮化HTO氧化物）的所有不透随后的热氧化的氧原子，的数的同时形成 在这个过程中的操作比现有技术的方法要小。