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公开(公告)号:EP3840039A1
公开(公告)日:2021-06-23
申请号:EP20213302.1
申请日:2020-12-11
Applicant: STMicroelectronics S.r.l.
Inventor: DERAI, Michele , TIZIANI, Roberto
IPC: H01L23/495
Abstract: A semiconductor device (10) comprises at least one semiconductor die (50) electrically coupled (54) to a set of electrically conductive leads, and package molding material (100) molded over the at least one semiconductor die (50) and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material (100) to provide electrically conductive pads (12, 44). The electrically conductive pads (12, 44) comprise enlarged end portions (44) extending at least partially over the package molding material (100) and configured for coupling to a printed circuit board (30).
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公开(公告)号:EP4181177A1
公开(公告)日:2023-05-17
申请号:EP22204387.9
申请日:2022-10-28
Applicant: STMicroelectronics S.r.l.
Inventor: DERAI, Michele , MAGNI, Pierangelo
IPC: H01L21/48 , H01L23/495 , H01L23/00
Abstract: A semiconductor device (10) comprises a semiconductor die (14) arranged on a substrate such as a leadframe (12A, 12B) and an encapsulation of laser direct structuring, LDS material (16; 161, 162) molded onto the semiconductor die (14).
A through mold via or TMV (182) extending through the encapsulation of LDS material (16; 161, 162) comprises:
an enlarged collar section (182A) that extends through a first portion (161) of the encapsulation (16) from an outer surface (1613) to an intermediate plane (1612) of the encapsulation (16), the enlarged collar section (182A) having a cross-sectional area at the intermediate plane (1612) of the encapsulation (16), and
a frusto-conical section (182B) that extends through a second portion (162) of the encapsulation (16; 161, 162) from a first end having a first diameter at the intermediate plane (1612) to a second end having a second diameter away from the intermediate plane (1612) of the encapsulation (16; 161, 162).
The first end of the frusto-conical section (182B) has an area smaller than the cross-sectional area of the enlarged collar section (182A) at the intermediate plane (1612) and the second diameter of the frusto-conical section (182B) is smaller than the first diameter of the frusto-conical section (182B). The through mold via (182) can thus have an aspect ratio which is not limited to 1:1.-
3.
公开(公告)号:EP3780074A2
公开(公告)日:2021-02-17
申请号:EP20191180.7
申请日:2020-08-14
Applicant: STMicroelectronics S.r.l.
Inventor: ZIGLIOLI, Federico Giovanni , PINTUS, Alberto , DERAI, Michele , MAGNI, Pierangelo
IPC: H01L21/56 , H01L21/60 , H01Q1/22 , H01L23/552 , H01L23/36
Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).-
公开(公告)号:EP4312239A1
公开(公告)日:2024-01-31
申请号:EP23186653.4
申请日:2023-07-20
Applicant: STMicroelectronics S.r.l.
Inventor: HALICKI, Damian , DERAI, Michele
Abstract: Semiconductor devices of the type currently referred to as a System in a Package or SiP and having embedded therein a transformer are produced by embedding at least one semiconductor chip (14) in an insulating encapsulation (180) at a first portion thereof.
Over a second portion of the substrate at least partly non-overlapping with the first portion of the substrate (180) having the at least one semiconductor chip (14) embedded therein, stacked structure is formed including a plurality of layers of electrically insulating material (Ll, L2, L3, L4) as well as respective patterns of electrically conductive material. The respective patterns of electrically conductive material have:
a planar coil geometry, thus providing electrically conductive coils such as the windings of a transformer (181, 182) or
a geometrical distribution providing electrically conductive connections to one or more semiconductor chips (14).-
公开(公告)号:EP4016590A1
公开(公告)日:2022-06-22
申请号:EP21215260.7
申请日:2021-12-16
Applicant: STMicroelectronics S.r.l.
Inventor: FONTANA, Fulvio Vittorio , DERAI, Michele
IPC: H01L21/48 , H01L23/495
Abstract: A method of manufacturing semiconductor devices such as QFN-mr packages, for instance, comprises arranging (1001) one or more semiconductor chips or dice (2000) at a first surface of a leadframe (1000) and forming (1005) an insulating encapsulation onto the leadframe (1000) having the semiconductor chip(s) arranged thereon at the first surface of the leadframe. Etching (1006) is applied at a second surface of the leadframe (1000) opposed to the first surface in order provide electrical contacts having a distal (bottom) surface as well as well as flanks left uncovered by the insulating encapsulation. Etching at the second surface of the leadframe (1000) is via an etching mask (3000) covering the electrical contacts as well as at least one connecting bar electrically coupling a plurality of electrical contacts. The etching mask is removed (3001) and the electrical contacts (12) and the connecting bar(s) thus exposed are used as electroplating electrodes in (e.g., tin) electroplating (3002) of the distal surface and the flanks of the electrical contacts (12) with the connecting bar(s) finally removed (1009, 1009A) during device singulation, for instance.
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6.
公开(公告)号:EP3780074A3
公开(公告)日:2021-06-02
申请号:EP20191180.7
申请日:2020-08-14
Applicant: STMicroelectronics S.r.l.
Inventor: ZIGLIOLI, Federico Giovanni , PINTUS, Alberto , DERAI, Michele , MAGNI, Pierangelo
IPC: H01L21/56 , H01L21/60 , H01Q1/22 , H01L23/552 , H01L23/367 , H01L23/31
Abstract: A method of manufacturing semiconductor devices, such as integrated circuits comprises:
- providing a support surface (10),
- arranging one or more semiconductor dice (12) on the support surface (10),
- molding laser direct structuring (LDS) material (14) onto the support surface (10) having the semiconductor die/dice (12) arranged thereon,
- laser beam processing (L) the laser direct structuring material (14) molded onto the support surface (10) having the semiconductor die/dice (12) arranged thereon to provide electrically conductive formations (16) for the semiconductor die/dice (12) arranged on the support surface, and
- separating from the support surface (10) the semiconductor die/dice (12) provided with said electrically-conductive formations (16).
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