公开(公告)号：EP3026696A1

公开(公告)日：2016-06-01

申请号：EP15185529.3

申请日：2015-09-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： FONTANA, Fulvio Vittorio ,  TALLEDO, Jefferson

IPC: H01L21/56 ,  B81B7/00 ,  B81C1/00 ,  H01L23/498

CPC classification number: G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: A surface mounting device (50) has one body (6) of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region (15) carrying the body, a cap (20) and contact terminals (3). The base region (15) has a Young's modulus lower than 5 MPa. For forming the device, the body (6) is attached to a supporting frame (1) including contact terminals (3) and a die pad (2), separated by cavities; bonding wires (14) are soldered to the body (6) and to the contact terminals (3); an elastic material is molded so as to surround at least in part lateral sides of the body (6), fill the cavities of the supporting frame (1) and cover the ends of the bonding wires (14) on the contact terminals; and a cap (20) is fixed to the base region (15). The die pad (2) is then etched away.

Abstract translation: 一种表面安装装置（50）具有半导体材料的一个本体（6）：如ASIC，和围绕所述本体的封装件。 所述封装具有承载体上的基极区域（15），盖（20）和接触端子（3）。 基极区域（15）具有的杨氏模量小于5兆帕以下。 为了形成器件，所述主体（6）被附连到支撑框架（1）包括接触端子（3）和所述衬垫（2）中，由空腔分开; 接合线（14）被焊接到所述主体（6）和所述接触端子（3）; 弹性材料被模制，以便至少在所述主体的一部分的横向侧（6），填充所述支撑框架（1）的空腔中并覆盖在接触端子的键合线（14）的端部以包围; 和一个盖（20）被固定到所述基极区域（15）。 所述衬垫（2）随后蚀刻掉。

公开(公告)号：EP4273907A1

公开(公告)日：2023-11-08

申请号：EP23170401.6

申请日：2023-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio

IPC: H01L21/48 ,  H01L23/495

Abstract: One or more semiconductor chips are arranged (102) on a first surface of a substrate comprising electrically conductive formations such as an array of electrically conductive leads covered by a masking layer at a second surface opposite the first surface. The semiconductor chip or chips are coupled to electrically conductive leads in the array and an insulating encapsulation is molded on the semiconductor chip or chips arranged on the first surface of the substrate. The masking layer is selectively removed (110), e.g., via laser ablation, from one or more of the electrically conductive formations that are thus left uncovered by the masking layer. Etching (112) is applied to the second surface of the substrate so that the leads left uncovered by the masking layer are removed, thus increasing the creepage distance between those conductive formations that are left in place.

公开(公告)号：EP4057342A2

公开(公告)日：2022-09-14

申请号：EP22160653.6

申请日：2022-03-08

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： FONTANA, Fulvio Vittorio ,  BENELLI, Davide Maria ,  TALLEDO, Jefferson Sismundo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device (10), such as a QFN (Quad-Flat No-lead) package, comprises one or mode semiconductor chips (14) arranged on a surface of a leadframe (12). The semiconductor chip(s) is/are arranged at a die pad (12A) of the leadframe (12) and the leadframe has an array of electrically-conductive leads (12B) around the die pad (12A). The leads in the array have distal ends facing away from the die pad (12A) as well as recessed portions (120B) of the surface of the leadframe (12) at the distal ends of the leads in the array (12B),
Resilient material (1200) such as low elasticity modulus material is formed at the recessed portions (120B) at the distal ends of the leads in the array (12B), and an insulating encapsulation (18) is molded onto the semiconductor chip (s) arranged on the leadframe.
The resilient material (1200) is sandwiched between the insulating encapsulation (18) and the distal ends of the leads in the array (12B) at the recessed portions (120B) and facilitates flexibility of the leads (12B), making them suited for reliable soldering (110) to an insulated metal substrate (100).

公开(公告)号：EP3038144A1

公开(公告)日：2016-06-29

申请号：EP15200614.4

申请日：2015-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/498

Abstract: A process for manufacturing a surface-mount electronic device, including the steps of: forming a plurality of preliminary contact regions (30; 60; 90) of a sinterable material on a supporting structure (2); mechanically coupling a die (42; 72; 82) including a semiconductor body (44; 75) to the supporting structure (2); and sintering the sinterable material, in such a way that each preliminary contact region (30; 60; 90) forms a corresponding sintered preliminary contact (36; 66; 96).

Abstract translation: 一种用于制造工艺的表面安装型电子器件，包括以下步骤：形成初步接触区的多个A烧结能材料上的支撑结构（2）（30; 60 90）; 机械耦合的一个（42; 72; 82）包括一个半导体本体（44; 75）到所述支撑结构（2）; 和烧结检查的烧结材料能够在某种程度上确实每个初步接触区域（30; 60; 90）形成的烧结对应初步接触（36; 66; 96）。

公开(公告)号：EP4016590A1

公开(公告)日：2022-06-22

申请号：EP21215260.7

申请日：2021-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio ,  DERAI, Michele

IPC: H01L21/48 ,  H01L23/495

Abstract: A method of manufacturing semiconductor devices such as QFN-mr packages, for instance, comprises arranging (1001) one or more semiconductor chips or dice (2000) at a first surface of a leadframe (1000) and forming (1005) an insulating encapsulation onto the leadframe (1000) having the semiconductor chip(s) arranged thereon at the first surface of the leadframe. Etching (1006) is applied at a second surface of the leadframe (1000) opposed to the first surface in order provide electrical contacts having a distal (bottom) surface as well as well as flanks left uncovered by the insulating encapsulation. Etching at the second surface of the leadframe (1000) is via an etching mask (3000) covering the electrical contacts as well as at least one connecting bar electrically coupling a plurality of electrical contacts. The etching mask is removed (3001) and the electrical contacts (12) and the connecting bar(s) thus exposed are used as electroplating electrodes in (e.g., tin) electroplating (3002) of the distal surface and the flanks of the electrical contacts (12) with the connecting bar(s) finally removed (1009, 1009A) during device singulation, for instance.

公开(公告)号：EP3098841A1

公开(公告)日：2016-11-30

申请号：EP15201108.6

申请日：2015-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio

IPC: H01L23/00

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/97 ,  H01L2021/6027 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row (QFN_mr) type, comprising providing (110) a metal leadframe, in particular a copper leadframe, which includes a plurality of pads (12a), each of which is designed to receive the body (20; 20') of the device, the pads (12a) being separated from adjacent pads by one or more rows (R1, R2) of wire-bonding contacting areas (12), outermost rows (R2) from among the one or more rows of wire-bonding contacting areas (12) identifying, together with outermost rows corresponding to the adjacent pads, separation regions (23).
The process envisages:
- depositing (120) in the separation regions (23) beads of conductive soldering material (15) so as to join together wire-bonding contacting areas (12) corresponding to adjacent pads (12a);
- fixing (130) the devices (20) to the respective pads (12a); and
- carrying out (140) a thermal process designed to sinter or re-flow the beads of conductive soldering material (15) into soldered beads (15s).

Abstract translation: 一种用于制造表面贴装的半导体器件，在特定进程四方扁平无引线多行（QFN_mr）类型，包括：提供（110）一个金属引线框架，（尤其是铜引线框架，其包括焊盘中的多元 图12A），其中的每一个被设计成接收所述主体（20;该装置的20“），所述片（12a）通过丝焊接触区域的一行或多行（R1，R2）从相邻衬垫分开（12 ），从引线键合的接触区域（12）确定的所述一个或多个行中最外面的行（R2），具有最外的行对应的相邻的垫一起，分离区（23）。 该方法设想： - 存入（120）中的分离区域（23）导电焊接材料（15），从而丝焊接触区域一起加入（12），对应于相邻焊盘（12a）的珠粒; - 定影（130）的设备（20）到respectivement片（12a）; 和 - 执行（140）的热过程，旨在烧结或再流焊接导电材料（15）焊接到珠（15S）的珠粒。

公开(公告)号：EP4057342A3

公开(公告)日：2022-09-28

申请号：EP22160653.6

申请日：2022-03-08

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： FONTANA, Fulvio Vittorio ,  BENELLI, Davide Maria ,  TALLEDO, Jefferson Sismundo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device (10), such as a QFN (Quad-Flat No-lead) package, comprises one or mode semiconductor chips (14) arranged on a surface of a leadframe (12). The semiconductor chip(s) is/are arranged at a die pad (12A) of the leadframe (12) and the leadframe has an array of electrically-conductive leads (12B) around the die pad (12A). The leads in the array have distal ends facing away from the die pad (12A) as well as recessed portions (120B) of the surface of the leadframe (12) at the distal ends of the leads in the array (12B),
Resilient material (1200) such as low elasticity modulus material is formed at the recessed portions (120B) at the distal ends of the leads in the array (12B), and an insulating encapsulation (18) is molded onto the semiconductor chip (s) arranged on the leadframe.
The resilient material (1200) is sandwiched between the insulating encapsulation (18) and the distal ends of the leads in the array (12B) at the recessed portions (120B) and facilitates flexibility of the leads (12B), making them suited for reliable soldering (110) to an insulated metal substrate (100).

公开(公告)号：EP3772097A1

公开(公告)日：2021-02-03

申请号：EP20189128.0

申请日：2020-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

Abstract: A lead frame for an integrated electronic device (700), including: a die pad structure (110; 29,110; 310,450) of a first metallic material, including a die pad (110;310,450) and delimited by a top structure surface (103; 103,103'; 303, 452); and a top coating structure (112; 12',112; 312, 512) formed by a second metallic material and arranged on the top structure surface, the second material having an oxidation rate lower than the first material. The top coating structure leaves exposed a number of corner portions (117S; 217S; 457S) of the top structure surface.

公开(公告)号：EP3038144B1

公开(公告)日：2019-11-20

申请号：EP15200614.4

申请日：2015-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Fulvio Vittorio

IPC: H01L21/56 ,  H01L23/498