Non volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values
    1.
    发明公开
    Non volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values 审中-公开
    读电路,用于非易失性存储器单元,尤其是在低电源电压和高容量的负载

    公开(公告)号:EP1426965A1

    公开(公告)日:2004-06-09

    申请号:EP02425747.9

    申请日:2002-12-04

    CPC classification number: G11C7/062 G11C7/067 G11C11/5642 G11C16/28

    Abstract: The present invention relates to a sensing circuit (10, 100) for a memory cell (11) inserted between a first (Vdd) and a second voltage reference (GND) and connected, in correspondence with a first inner circuit node (XBL), to the memory cell (11) of the type comprising:

    a first bias current (Ip) generator (12) inserted between the first voltage reference (Vdd) and the first inner circuit node (XBL);
    a comparator (17) having a first input terminal (-) connected to a comparison circuit node (Xrif), connected in turn to the first voltage reference (Vdd) by means of at least a second reference current (Iref) generator (15), as well as a second input terminal (+) connected to a circuit node (Xmat) connected in turn to the first inner circuit node (XBL), an output terminal (OUT) of the comparator (17) corresponding to an output terminal of the sensing circuit (10).

    Advantageously according to the invention, the sensing circuit comprises also:

    a cascode-configured bias circuit (13) inserted between the inner circuit node (XBL) and the matching circuit node (Xmat) and connected to a third voltage reference (Vref); and
    a current/voltage conversion stage (16) connected to the matching circuit node (Xmat) and to the comparison circuit node (Xrif), as well as to the second voltage reference (GND).

    Abstract translation: 本发明涉及一种用于将第一(VDD)之间插入的存储单元(11)和第二电压基准(GND)和地连接,对应于第一内电路节点的感测电路(10,100)(XBL) 的类型,其包括存储单元(11):所述第一电压基准(VDD)和所述第一内电路节点(XBL)之间插入的第一偏置电流(Ip)发生器(12); 具有第一输入端的比较器(17)( - )连接到由至少一个第二参考电流的手段比较电路节点(Xrif),依次连接到所述第一参考电压(VDD)(IREF)发生器(15) ,以及一第二输入端(+)连接到又连接到所述第一内电路节点(XBL)到比较器的输出端(OUT)(17)的电路节点(XMAT)对应于到的输出端子 感测电路(10)。 有利地雅丁到本发明,所述传感电路包括即:插入所述内电路节点(XBL)和匹配电路节点(XMAT)之间并且连接到第三电压参考一个共源共栅配置的偏置电路(13)( VREF); 和连接到该匹配电路节点(XMAT)和所述比较电路节点(Xrif)的电流/电压转换级(16),以及所述第二电压基准(GND)。

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