Abstract:
The present invention relates to a sensing circuit (10, 100) for a memory cell (11) inserted between a first (Vdd) and a second voltage reference (GND) and connected, in correspondence with a first inner circuit node (XBL), to the memory cell (11) of the type comprising:
a first bias current (Ip) generator (12) inserted between the first voltage reference (Vdd) and the first inner circuit node (XBL); a comparator (17) having a first input terminal (-) connected to a comparison circuit node (Xrif), connected in turn to the first voltage reference (Vdd) by means of at least a second reference current (Iref) generator (15), as well as a second input terminal (+) connected to a circuit node (Xmat) connected in turn to the first inner circuit node (XBL), an output terminal (OUT) of the comparator (17) corresponding to an output terminal of the sensing circuit (10).
Advantageously according to the invention, the sensing circuit comprises also:
a cascode-configured bias circuit (13) inserted between the inner circuit node (XBL) and the matching circuit node (Xmat) and connected to a third voltage reference (Vref); and a current/voltage conversion stage (16) connected to the matching circuit node (Xmat) and to the comparison circuit node (Xrif), as well as to the second voltage reference (GND).