公开(公告)号：EP1519489A1

公开(公告)日：2005-03-30

申请号：EP03021455.5

申请日：2003-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

IPC: H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

Abstract: The present invention proposes a Field Programmable Gate Array (FPGA) device (100) comprising a plurality of configurable electrical connections (115 1 -115 2 ,115 1 -115 3 ), a plurality of controlled switches (205), each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit (125) including an arrangement of a plurality of control cells (200). Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element (210,215) adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element (P1;F1) coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract translation: 本发明提出了一种包括多个可配置电连接（1151-1152,1151-1153）的现场可编程门阵列（FPGA）装置，多个受控开关（205），每个控制开关适于启动/ 响应于开关控制信号激活至少一个相应的电连接，以及包括多个控制单元（200）的布置的控制单元（125）。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件（210,215），其适于以易失性方式存储对应于至少一个 控制开关，并且向控制开关提供与存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件（P1; F1），非易失性存储元件适于以非易失性方式存储控制逻辑值。

公开(公告)号：EP1435621A1

公开(公告)日：2004-07-07

申请号：EP02425809.7

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Iezzi, David ,  Muzzi, Gilberto ,  Poles, Marco

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G06F1/26 ,  G11C5/145

Abstract: The invention relates to an architecture for distributing supply voltages to a plurality of memory modules (Mod1, ..., ModN) supplied through a plurality of charge pump circuits (Pump1, ..., PumpM).
Advantageously according to the invention, the architecture for distributing supply voltages comprises a sorting block (11) bidirectionally-connected to the plurality of memory modules (Mod1, ..., ModN) from which it receives a plurality of power requests and it is capable of providing a sorting signal (ORD) of said power requests on the basis of a priority scale in order to drive the plurality of charge pump circuits (Pump1, , PumpM) and distribute convenient supply voltages (Vhigh1, ..., VhighN; Vneg1, ..., VnegN) to the plurality of memory modules (Mod1, ..., ModN). Moreover, this architecture is software-configurable.

Abstract translation: 本发明涉及一种用于向通过多个电荷泵电路（Pump1，...，PumpM）提供的多个存储器模块（Mod1，...，ModN）分配电源电压的架构。 有利地，根据本发明，用于分配电源电压的架构包括双向连接到多个存储器模块（Mod1，...，ModN）的分类块（11），从该存储器模块接收多个电力请求 并且能够基于优先级来提供所述功率请求的分类信号（ORD），以驱动多个电荷泵电路（Pump1，PumpM）并且分配方便的电源电压（Vhigh1，...） ，VhighN; Vneg1，...，VnegN）连接到多个存储器模块（Mod1，...，ModN）。 而且，这种架构是软件可配置的。

公开(公告)号：EP1215679A1

公开(公告)日：2002-06-19

申请号：EP01129768.6

申请日：2001-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Pasotti, Marco ,  Rolandi, Pier Luigi ,  Guaitini, Giovani ,  Iezzi, David ,  Poles, Marco

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C17/146

Abstract: The invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), which method comprises the phases of:

initially programming (I) a cell threshold value (VthDATI) to a first set of levels [O;(m-1)] being (m) a submultiple of the plurality (N) of levels of the multilevel cell;
reprogramming without erasing (II) another set of levels [m;(2m-1)] containing the same number of levels (m) as the first set;
reiterating (N R - 1 times) the reprogramming without erasing phase (III,IV, ...) until the levels (N) of the multilevel cell are exhausted.

The invention makes also reference to a multilevel memory device of the type comprising a plurality. of multilevel memory cells organised into sectors, the sectors being themselves split into a plurality of data units (UD) wherein a data updating operation is performed in parallel, the data units (UD) being programmed by means of the programming method according to the invention.

Abstract translation: 本发明涉及一种能够存储多个级别（N）中的多个位的多级存储器单元的编程方法，该方法包括以下阶段：首先将单元阈值（VthDATI）编程（I）到第一 层级ÄO;（m-1）Ü是（m）多级单元的多（N）个级别中的一个子; 重新编程而不擦除（II）另一组水平Äm;（2m-1）Ü包含与第一组相同数量的水平（m）; 重复（NR-1次）重编程而不擦除相位（III，IV，...），直到多级单元的电平（N）耗尽。 本发明还涉及包括多个类型的多级存储器件。 的多级存储器单元被组织成扇区，扇区本身被分成多个数据单元（UD），其中并行执行数据更新操作，数据单元（UD）通过根据本发明的编程方法进行编程 。

公开(公告)号：EP1324342B1

公开(公告)日：2008-07-16

申请号：EP01830827.0

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Poles, Marco ,  Iezzi, David ,  Pasotti, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5641

公开(公告)号：EP1435621B1

公开(公告)日：2007-07-11

申请号：EP02425809.7

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Iezzi, David ,  Muzzi, Gilberto ,  Poles, Marco

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G06F1/26 ,  G11C5/145

公开(公告)号：EP1426965A1

公开(公告)日：2004-06-09

申请号：EP02425747.9

申请日：2002-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： De Santis, Fabio ,  Pasotti, Marco ,  De Sandre, Guido

IPC: G11C7/06 ,  G11C16/28 ,  G11C11/56

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28

Abstract: The present invention relates to a sensing circuit (10, 100) for a memory cell (11) inserted between a first (Vdd) and a second voltage reference (GND) and connected, in correspondence with a first inner circuit node (XBL), to the memory cell (11) of the type comprising:

a first bias current (Ip) generator (12) inserted between the first voltage reference (Vdd) and the first inner circuit node (XBL);
a comparator (17) having a first input terminal (-) connected to a comparison circuit node (Xrif), connected in turn to the first voltage reference (Vdd) by means of at least a second reference current (Iref) generator (15), as well as a second input terminal (+) connected to a circuit node (Xmat) connected in turn to the first inner circuit node (XBL), an output terminal (OUT) of the comparator (17) corresponding to an output terminal of the sensing circuit (10).

Advantageously according to the invention, the sensing circuit comprises also:

a cascode-configured bias circuit (13) inserted between the inner circuit node (XBL) and the matching circuit node (Xmat) and connected to a third voltage reference (Vref); and
a current/voltage conversion stage (16) connected to the matching circuit node (Xmat) and to the comparison circuit node (Xrif), as well as to the second voltage reference (GND).

Abstract translation: 本发明涉及一种用于将第一（VDD）之间插入的存储单元（11）和第二电压基准（GND）和地连接，对应于第一内电路节点的感测电路（10，100）（XBL） 的类型，其包括存储单元（11）：所述第一电压基准（VDD）和所述第一内电路节点（XBL）之间插入的第一偏置电流（Ip）发生器（12）; 具有第一输入端的比较器（17）（ - ）连接到由至少一个第二参考电流的手段比较电路节点（Xrif），依次连接到所述第一参考电压（VDD）（IREF）发生器（15） ，以及一第二输入端（+）连接到又连接到所述第一内电路节点（XBL）到比较器的输出端（OUT）（17）的电路节点（XMAT）对应于到的输出端子 感测电路（10）。 有利地雅丁到本发明，所述传感电路包括即：插入所述内电路节点（XBL）和匹配电路节点（XMAT）之间并且连接到第三电压参考一个共源共栅配置的偏置电路（13）（ VREF）; 和连接到该匹配电路节点（XMAT）和所述比较电路节点（Xrif）的电流/电压转换级（16），以及所述第二电压基准（GND）。

公开(公告)号：EP1220228A1

公开(公告)日：2002-07-03

申请号：EP00830866.0

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Guaitini, Giovanni ,  Iezzi, David ,  Poles, Marco ,  Rolandi, PierLuigi

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

Abstract translation: 这里描述了一种用于将数据存储在非易失性存储器的第一和第二存储单元中的方法。 存储方法设想通过在第一存储单元中设置第一阈值电压和与第二存储单元中的第一阈值电压不同的第二阈值电压来以差分方式对第一和第二存储单元进行编程，阈值电压 表示存储在存储单元本身中的数据的两个存储器单元。

公开(公告)号：EP1519489B1

公开(公告)日：2009-05-06

申请号：EP03021455.5

申请日：2003-09-23

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  De Sandre, Guido ,  Bez, Roberto

IPC: H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

公开(公告)号：EP1526547A1

公开(公告)日：2005-04-27

申请号：EP03103898.7

申请日：2003-10-22

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

公开(公告)号：EP1324342A1

公开(公告)日：2003-07-02

申请号：EP01830827.0

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Poles, Marco ,  Iezzi, David ,  Pasotti, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5641

Abstract: The invention relates to a programming method of a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), the method comprising at least a step of writing a logic value in the multilevel memory cell by setting one of the programming levels (LA) thereof, these levels being included in the plurality of levels (N), with respect to a reference level (LR) according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value (Lmax) for the levels (LS, LR) is reached.
The invention relates also to a multilevel memory device comprising a plurality of multilevel memory cells organised into sectors, split into a plurality of data units (UD) whereon a programming operation is performed in parallel according to the method of the invention.

Abstract translation: 本发明涉及能够存储多个电平（N）中的多个位的多电平存储器单元的编程方法，所述方法至少包括以下步骤：通过将所述多电平存储器单元 编程电平（LA），这些电平相对于根据要写入的符号的参考电平（LR）和先前的编程电平被包括在多个电平（N）中。 重复写入步骤直到达到电平（LS，LR）的最高可能值（Lmax）。 本发明还涉及一种多级存储器件，其包括被组织成扇区的多个多电平存储器单元，分成多个数据单元（UD），根据本发明的方法并行执行编程操作。