公开(公告)号：EP0907201A1

公开(公告)日：1999-04-07

申请号：EP97830491.3

申请日：1997-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： DeSanti, Giorgio ,  Zanotti, Luca ,  Bacchetta, Maurizio Emanuele

IPC: H01L21/3105

CPC classification number: H01L21/31053 ,  H01L21/31051

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), said devices comprising a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, into said trench regions (3), of a dielectric ply structure comprising a first layer (4) of oxide and a second layer (5) of oxide deposited over said first layer (4). Said first layer (4) is formed by high density plasma chemical vapor deposition (HDP-CVD) and said second layer (5) is a doped silicon oxide. A planarizing step is further applied by chemio-mechanical polishing (CMP) of said second layer (5).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面性的平面化方法，所述器件包括由栅极区（2）形成的多个有源元件，栅极区（2）以衬底（1）表面为突出且限定沟槽区（3 ）之间。 该方法提供了在所述沟槽区域（3）中沉积电介质片层结构，该电介质片层结构包括氧化物的第一层（4）和沉积在所述第一层（4）上的第二氧化物层（5）。 所述第一层（4）由高密度等离子体化学气相沉积（HDP-CVD）形成，所述第二层（5）为掺杂氧化硅。 通过所述第二层（5）的化学机械抛光（CMP）进一步施加平面化步骤。

公开(公告)号：EP0907202A1

公开(公告)日：1999-04-07

申请号：EP98105777.1

申请日：1998-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： DeSanti, Giorgio ,  Zanotti, Luca ,  Bacchetta, Maurizio Emanuele

IPC: H01L21/3105

CPC classification number: H01L21/31053

Abstract: A planarization method for improving the planarity of electronic devices integrated on a semiconductor substrate (1), said devices comprising a plurality of active elements formed with gate regions (2) which stand proud of the substrate (1) surface and define trench regions (3) therebetween. The method provides for the deposition, into said trench regions (3), of a dielectric stack structure comprising a first layer (4) of oxide and a second layer (5) of oxide deposited over said first layer (4). Said first layer (4) is formed by high density plasma chemical vapor deposition (HDP-CVD) and said second layer (5) is a doped silicon oxide. A planarizing step is further applied by chemical-mechanical polishing (CMP) of said second layer (5).

Abstract translation: 一种用于改善集成在半导体衬底（1）上的电子器件的平面性的平面化方法，所述器件包括形成有栅极区域（2）的多个有源元件，所述栅极区域（2）以衬底（1）表面为傲，并且限定沟槽区域 ）。 该方法提供了在所述沟槽区域（3）中沉积包括氧化物的第一层（4）和沉积在所述第一层（4）上的氧化物的第二层（5））的介电堆叠结构。 所述第一层（4）通过高密度等离子体化学气相沉积（HDP-CVD）形成，所述第二层（5）是掺杂的氧化硅。 通过所述第二层（5）的化学机械抛光（CMP）进一步应用平坦化步骤。