公开(公告)号：EP1626411A1

公开(公告)日：2006-02-15

申请号：EP04425631.1

申请日：2004-08-13

Applicant: STMicroelectronics S.r.l.

Inventor： Dennison, Charles ,  Lowrey, Tyler

IPC: G11C11/34 ,  G11C5/02

CPC classification number: G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

Abstract: A crosspoint memory (10) includes a shared address line (12). The shared address line may be coupled to cells (14, 16) above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract translation: 交叉点存储器（10）包括共享地址线（12）。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的小区（14,16）。 可以利用电压偏压来选择一个电池，并且取消选择另一个电池。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造和降低成本。

公开(公告)号：EP1801896A1

公开(公告)日：2007-06-27

申请号：EP05112912.0

申请日：2005-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Dennison, Charles ,  Peters, John

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1675

Abstract: In a phase change memory including an ovonic threshold switch, conduction around the chalcogenide layer (22) in the ovonic threshold switch is reduced. In one embodiment, the reduction is achieved by undercutting the conductive layers (18,26) on either side of the chalcogenide layer (22). In another embodiment, an angled ion implantation is carried out which damages the edge regions (18b,16b) of the conductive layers (18,26) that sandwich the chalcogenide layer (22).