Abstract:
A phase-change memory device includes a plurality of data PCM cells (13), for storing data bits; data decoding circuits (14, 27, 28a), for selectively addressing sets of data PCM cells (13); and data read/program circuits (20a), for reading and programming the selected data PCM cells (13). The device further includes a plurality of parity PCM cells (25), for storing parity bits associated to data bits stored in the data PCM cells (13); parity decoding circuits (14, 27, 28b), for selectively addressing sets of parity PCM cells (25); and parity read/program circuits (20b), for reading and programming the selected parity PCM cells (25).
Abstract:
A phase-change memory device includes a plurality of data PCM cells (13), for storing data bits; data decoding circuits (14, 27, 28a), for selectively addressing sets of data PCM cells (13); and data read/program circuits (20a), for reading and programming the selected data PCM cells (13). The device further includes a plurality of parity PCM cells (25), for storing parity bits associated to data bits stored in the data PCM cells (13); parity decoding circuits (14, 27, 28b), for selectively addressing sets of parity PCM cells (25); and parity read/program circuits (20b), for reading and programming the selected parity PCM cells (25).