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    Phase-change memory device with error correction capability
    1.
    发明公开
    Phase-change memory device with error correction capability 审中-公开
    Phasenwechsel-Speichervorrichtung mit Fehlerkorrekturfunktion

    公开(公告)号：EP1947652A1

    公开(公告)日：2008-07-23

    申请号：EP07425569.6

    申请日：2007-09-13

    Applicant: STMicroelectronics S.r.l.

    Inventor： Donze, Enzo Michele ,  Bedeschi, Ferdinando ,  Jagasivamani, Meenatchi

    IPC: G11C29/52 ,  G11C16/02 ,  G11C13/02 ,  G06F11/10

    CPC classification number: B01F7/04 ,  B01F7/00258 ,  B01F7/00425 ,  B01F13/06 ,  B01F2015/0221 ,  G06F11/1068 ,  G11C13/02

    Abstract: A phase-change memory device includes a plurality of data PCM cells (13), for storing data bits; data decoding circuits (14, 27, 28a), for selectively addressing sets of data PCM cells (13); and data read/program circuits (20a), for reading and programming the selected data PCM cells (13). The device further includes a plurality of parity PCM cells (25), for storing parity bits associated to data bits stored in the data PCM cells (13); parity decoding circuits (14, 27, 28b), for selectively addressing sets of parity PCM cells (25); and parity read/program circuits (20b), for reading and programming the selected parity PCM cells (25).

    Abstract translation: 相变存储器件包括用于存储数据位的多个数据PCM单元（13）; 数据解码电路（14,27,28a），用于选择性寻址数据PCM单元（13）; 和数据读取/编程电路（20a），用于读取和编程所选择的数据PCM单元（13）。 该装置还包括多个奇偶校验PCM单元（25），用于存储与存储在数据PCM单元（13）中的数据位相关联的奇偶校验位; 奇偶校验解码电路（14,27,28b），用于选择性地寻址奇偶校验PCM单元（25）组; 以及用于读取和编程所选奇偶校验PCM单元（25）的奇偶校验读/写电路（20b）。

    A memory device with unipolar and bipolar selectors
    2.
    发明公开
    A memory device with unipolar and bipolar selectors 有权
    Speiherannnung mit unipolaren和bipolaren Auswahlschaltungen

    公开(公告)号：EP1640994A1

    公开(公告)日：2006-03-29

    申请号：EP04104595.6

    申请日：2004-09-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Benvenuti, Augusto ,  Vendrame, Loris ,  Zuliani, Paola

    IPC: G11C16/02 ,  G11C11/34

    CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    Abstract translation: 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。

    Phase-change memory device with biasing of deselected bit lines
    3.
    发明公开
    Phase-change memory device with biasing of deselected bit lines 有权
    Ph en en en en en en en en en en en en en en en en en en en

    公开(公告)号：EP1511042A1

    公开(公告)日：2005-03-02

    申请号：EP03077667.8

    申请日：2003-08-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio

    IPC: G11C11/34

    CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

    Abstract: A memory device (100) is proposed. The memory device includes a matrix (105) of memory cells (P h,k ,T h,k ) arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element (P h,k ) with a programmable resistivity and a unidirectional conduction access element (T h,k ) connected in series, a plurality of word lines (WL h ) and a plurality of bit lines (BL k ), the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means (120) for driving the bit lines to a desired voltage, means (110c,115) for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means (110r) for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means (Pd h ,Td h ;B k ,Bd,205,S k ,Sd;D k ,Dd,303-320) for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.

    Abstract translation: 提出了一种存储装置（100）。 存储器件包括排列成多行和多列的存储单元（Ph，k，Th，k）的矩阵（105），每个存储单元包括具有可编程电阻率的功能元件（Ph，k） 串行连接的单向导通接入元件（Th，k），多个字线（WLh）和多个位线（BLk），每行的存储单元连接到相应的字线，并且存储单元 每列连接到对应的位线，用于将位线驱动到期望电压的装置（120），用于在存储器件的操作状态中选择至少一个位线的装置（110c，115），每个选择的位线 连接到用于驱动的​​装置和每个取消选择的位线与用于驱动的​​装置断开;以及用于在操作状态中选择字线的装置（110r），与所选择的字线和所选择的至少一个所选择的字线相关联的每个存取元件 位线正向b 其他访问元素被反向偏移; 存储器件还包括用于在操作状态下偏置未选位线的装置（Pdh，Tdh; Bk，Bd，205，Sk，Sd; Dk，Dd，303-320），以防止反向偏置访问元件 从正向偏置与所选择的字线和取消选择的位线相关联的存取元件。

    Fast reading, low power consumption memory device and reading method thereof
    5.
    发明公开
    Fast reading, low power consumption memory device and reading method thereof 有权
    存储器阵列具有快速读出操作和更低的功耗和相应的读出方法

    公开(公告)号：EP1548745A1

    公开(公告)日：2005-06-29

    申请号：EP04106858.6

    申请日：2004-12-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C8/10 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C8/08

    Abstract: A memory device having a reading configuration and including a plurality of memory cells (3), arranged in rows and columns, memory cells (3) arranged on the same column having respective first terminals (3a) connected to a same bit line (12) and memory cells (3) arranged on the same row having respective second terminals (3b) selectively connectable to a same word line (13); a supply line (9) providing a supply voltage (V DD ); a column addressing circuit (4) and a row addressing circuit (5) for respectively addressing a bit line (12) and a word line (13) corresponding to a memory cell (3) selected for reading in the reading configuration. The column addressing circuit (4) is configured to bias the addressed bit line (12) corresponding to the selected memory cell (3) substantially at the supply voltage (V DD ) in the reading configuration. A row driving circuit (6) biases the addressed word line (13) corresponding to the selected memory cell (3) at a non-zero word line read voltage (V WL ), so that a predetermined cell voltage (V CELL ), lower than a phase change voltage (V PHC ), is applied between the first terminal (3a) and the second terminal (3b) of the selected memory cell (3) in the reading configuration.

    Abstract translation: 具有读取配置和包含存储单元的多个（3），以行和列排列的存储器单元的存储器装置（3）布置在具有连接到相同的位线respectivement第一端子（3a）中同一列（12）中 和存储单元（3），布置在同一行上具有respectivement第二端子（3b）中选择性地连接到一个相同的字线（13）; 一电源线（9）提供电源电压（VDD）; 一列寻址电路（4）和用于分别寻址的位线（12）和字线（13）的行寻址电路（5）对应于一个存储单元（3）选择用于在读取配置读取。 列寻址电路（4）被配置为偏置对应于所选择的存储单元的寻址位线（12）（3）在基本上在读取配置中的电源电压（VDD）。 行驱动电路（6）偏压对应于所述选定存储器单元被寻址的字线（13）（3）在非零字线读取电压（VWL），所以没有在预定的电池电压（V电池），比下 相变电压（VPHC）在第一端（3a）和在读取配置所述选定存储器单元（3）的第二端（3b）的之间。

    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
    6.
    发明公开
    Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations 有权
    非易失性的相变存储器的单电源电压，共源共栅列选择和同时读取和写入操作Wortlese-

    公开(公告)号：EP1326258A3

    公开(公告)日：2004-10-13

    申请号：EP02028616.7

    申请日：2002-12-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando

    IPC: G11C16/24 ,  G11C16/02

    CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C7/22 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2216/22

    Abstract: A nonvolatile memory device (10'; 10") is described comprising a memory array (11), a row decoder (12) and a column selector (13) for addressing the memory cells (16) of the memory array (11), and a biasing stage (22; 36, 28) for biasing the array access device terminal of the addressed memory cell (16). The biasing stage (22; 36 28) is arranged between the column selector (13) and the memory array (11) and comprises a biasing transistor (22; 36) having a drain terminal connected to the column selector (13), a source terminal connected to the array access device terminal of the addressed memory cell (16), and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block (31) and an output buffer (32) cascaded together. The output buffer (32) may be supplied with either a read voltage (VREAD) or a program voltage (VPROG) supplied by a multiplexer (33). The biasing transistor (22; 36) may be either included as part of the column selector (13) and formed by the selection transistor (22) which is closest to the addressed memory cell (16) or distinct from the selection transistors (20, 21, 22) of the column selector (13).

    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages
    9.
    发明公开
    Phase change memory device with overvoltage protection and method for protecting a phase change memory device against overvoltages 有权
    相变存储器以浪涌保护和保护方法，用于相变存储器与浪涌保护

    公开(公告)号：EP1538632A1

    公开(公告)日：2005-06-08

    申请号：EP03425728.7

    申请日：2003-11-12

    Applicant: STMicroelectronics S.r.l. ,  Universita' Degli Studi Di Pavia

    Inventor： Bedeschi, Ferdinando ,  Resta, Claudio ,  Torelli, Guido

    IPC: G11C11/34 ,  G11C7/12

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: A phase change memory device includes a plurality of PCM cells (3), arranged in rows and columns, PCM cells (3) arranged on the same column being connected to a same bit line (10); a plurality of first selectors (12), each coupled to a respective PCM cell (3); an addressing circuit (4, 5) for selectively addressing at least one of the bit lines (10), one of the first selectors (12), and the PCM cell (3) connected to the addressed bit line (10) and to the addressed first selector (12); and a regulated voltage supply circuit (7, 14, 15), selectively connectable to the addressed bit line (10), for supplying a bit line voltage (V BL ). The bit line voltage (V BL ) is correlated to a first control voltage (V EBA ) on the addressed first selector (12), coupled to the addressed PCM cell (3).

    Abstract translation: 一种相变存储器装置包括PCM单元的多个（3），以行和列布置，PCM单元（3）布置在相同的列被连接到相同的位线（10）; 第一选择器的多个（12），每个耦合到respectivement PCM单元（3）; 在用于选择性地寻址所述位线中的至少一个（10）中，第一选择器中的一个（12）和所述PCM单元寻址电路（4,5）（3）连接到所寻址的位线（10）和所述 寻址第一选择器（12）; 和经调节的电压供给电路（7，14，15）选择性地连接到用于供给位线电压（VBL）被寻址的位线（10）。 位线电压（VBL）被关联以在被寻址第一选择器（12），耦合到所寻址的PCM单元（3）的第一控制电压（VEBA）。

    Architecture of a phase-change nonvolatile memory array
    10.
    发明公开
    Architecture of a phase-change nonvolatile memory array 有权
    建筑工人工程师协会

    公开(公告)号：EP1326254A1

    公开(公告)日：2003-07-09

    申请号：EP01830806.4

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Bedeschi, Ferdinando ,  Bosisio, Giorgio ,  Pellizzer, Fabio

    IPC: G11C11/34

    CPC classification number: G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: The phase-change nonvolatile memory array (8) is formed by a plurality of memory cells (10, 10') extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines (11) extend parallel to the first direction. A plurality of word-selection lines (12) extend parallel to the second direction. Each memory cell (10, 10') includes a PCM storage element (15) and a selection transistor (16). A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line (12). A second terminal of the PCM storage element (15) is connected to a respective column-selection line (11), and a second terminal of the selection transistor (16) is connected to a reference-potential region (18) while reading and programming the memory cells (10, 10').

    Abstract translation: 相变非易失性存储器阵列（8）由在彼此正交的第一和第二方向上延伸的多个存储单元（10,10'）形成。 多个列选择线（11）平行于第一方向延伸。 多个字选择线（12）平行于第二方向延伸。 每个存储单元（10,10'）包括PCM存储元件（15）和选择晶体管（16）。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线（12）。 PCM存储元件（15）的第二端子连接到相应的列选择线（11），并且选择晶体管（16）的第二端子连接到参考电位区域（18），同时读取和编程 存储单元（10,10'）。

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