公开(公告)号：EP2244299A1

公开(公告)日：2010-10-27

申请号：EP10160716.6

申请日：2010-04-22

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Gattari, Paolo ,  Paleari, Andrea ,  Dundulachi, Alessandro

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/42368 ,  H01L29/7835

Abstract: A MOS transistor (100) for power applications in a substrate (105) of semiconductor material, is formed by a method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element (127) on a top surface (112) of the substrate and forming a control electrode (128) on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. Said insulating element comprises a first portion (130) and a second portion (135). The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element comprises generating said second portion by locally oxidizing the top surface.

Abstract translation: 在半导体材料的基板（105）功率应用的MOS晶体管（100），通过被集成在用于制造STI技术的用于形成绝缘区使用的集成电路的工艺的方法形成。 该方法包括在基片上的一个顶面（112）的绝缘元件（127）和形成在所述绝缘元件的自由表面上的控制电极（128）的成形的相位。 绝缘元件从绝缘基片上的控制电极。 所述绝缘元件包括第一部分（130）和第二部分（135）。 沿第一方向的第一部分的垂直于顶面的延伸小于所述第二部分的延伸沿寻求第一方向低。 形成绝缘元件的相包括生成通过局部氧化的顶表面，所述第二部分。