公开(公告)号：EP1148555A1

公开(公告)日：2001-10-24

申请号：EP00830308.3

申请日：2000-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/08

CPC classification number: H01L29/0878 ,  H01L29/7816

Abstract: A RESURF LDMOS integrated structure realized in a first region (drain well) of a first type of conductivity defined in a semiconductor substrate of opposite type of conductivity and comprising a source region of said first type of conductivity formed in a body region of said opposite type of conductivity. Said body region is contained within a surface portion (body buffer region) of the first region that is more heavily doped than the rest of the region to avoid punch-through when the structure operates as a high side driver.

Abstract translation: RESURF LDMOS集成结构，其实现于在相反导电类型的半导体衬底中限定的第一类型导电体的第一区域（漏极阱）中，并且包括形成在所述相反类型的体区域中的所述第一类型的导电源的源极区域 的电导率。 所述体区域包含在比其余区域更重掺杂的第一区域的表面部分（体缓冲区域）中，以避免当该结构作为高侧驱动器时起作用。

公开(公告)号：EP1158583A1

公开(公告)日：2001-11-28

申请号：EP00830373.7

申请日：2000-05-23

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Moscatelli, Alessandro ,  Merlini, Alessandra ,  Galbiati, Paola

IPC: H01L29/78 ,  H01L29/417

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456

Abstract: An LDMOS structure is realized in a region of a first type of conductivity (N-POCKET) of a semiconductor substrate and comprises a gate, a drain region and a source region, the latter being constituted by a body diffusion (PBODY) of a second type of conductivity within said first region (N-POCKET), a source diffusion (N + ) of said first type of conductivity within said body diffusion (PBODY); an electrical connection diffusion (P + ) of said second type of conductivity, in a limited area of said source region, extending through said source diffusion (N + ) and reaching down to said body diffusion (PBODY), at least a source contact on said source diffusion (N + ) and said electrical connection diffusion (P + ), and further comprises a layer of silicide over the whole area of the source region short-circuiting said source diffusion (N + ) and said electrical connection diffusion (P + ); said source contact being established on said silicide layer.

Abstract translation: LDMOS结构在半导体衬底的第一导电类型（N-POCKET）的区域中实现并且包括栅极，漏极区域和源极区域，后者由第二导电类型的体扩散（PBODY） 所述第一区域内的导电类型（N-POCKET），所述体扩散（PBODY）内所述第一导电类型的源极扩散（N +）; 在所述源极区域的有限区域中的所述第二类型导电性的电连接扩散（P +）延伸穿过所述源极扩散（N +）并到达所述体扩散（PBODY），所述源极上的至少源极接触 扩散（N +）和所述电连接扩散（P +），并且还包括在源区的整个区域上短路所述源扩散（N +）和所述电连接扩散（P +）的硅化物层; 所述源极触点建立在所述硅化物层上。

公开(公告)号：EP2244299A1

公开(公告)日：2010-10-27

申请号：EP10160716.6

申请日：2010-04-22

Applicant: STMicroelectronics S.r.l.

Inventor： Croce, Giuseppe ,  Gattari, Paolo ,  Paleari, Andrea ,  Dundulachi, Alessandro

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/42368 ,  H01L29/7835

Abstract: A MOS transistor (100) for power applications in a substrate (105) of semiconductor material, is formed by a method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element (127) on a top surface (112) of the substrate and forming a control electrode (128) on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. Said insulating element comprises a first portion (130) and a second portion (135). The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element comprises generating said second portion by locally oxidizing the top surface.

Abstract translation: 在半导体材料的基板（105）功率应用的MOS晶体管（100），通过被集成在用于制造STI技术的用于形成绝缘区使用的集成电路的工艺的方法形成。 该方法包括在基片上的一个顶面（112）的绝缘元件（127）和形成在所述绝缘元件的自由表面上的控制电极（128）的成形的相位。 绝缘元件从绝缘基片上的控制电极。 所述绝缘元件包括第一部分（130）和第二部分（135）。 沿第一方向的第一部分的垂直于顶面的延伸小于所述第二部分的延伸沿寻求第一方向低。 形成绝缘元件的相包括生成通过局部氧化的顶表面，所述第二部分。

公开(公告)号：EP1347511A1

公开(公告)日：2003-09-24

申请号：EP02425179.5

申请日：2002-03-22

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Alessandro ,  Croce, Giuseppe

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823857

Abstract: A method for manufacturing a MOS transistor integrated into a chip (2) of semi-conductive material comprising a first (D-REG) and a second (S-REG) active region which extend from the inside of the chip to a surface (7) of the chip. The method comprises the steps of:

a) forming a layer of insulating material (13) on the surface (7) of the chip (2) and deposition of a layer of conductive material (14) on said insulating layer,
b) defining a insulated gate electrode (INS-G) of the transistor, starting from said superimposed insulating (13) and conductive (14) layers,
   characterized in that it also comprises the steps of:
c) defining, starting from said superimposed insulating (13) and conductive (14) layers, an additional structure (ADD-STR) arranged on a first surface portion (N-well) of the first active region (D-REG),
d) placing between the insulated gate electrode (INS-G) and the additional structure (ADD-STR) a dielectric spacer (C-SP) placed on a second surface portion (17) of the first active region (D-REG).

Abstract translation: 一种集成到半导体材料芯片（2）中的MOS晶体管的制造方法，包括从芯片的内部延伸到表面（7）的第一（D-REG）和第二（S-REG）有源区 ）的芯片。 该方法包括以下步骤：a）在所述芯片（2）的表面（7）上形成绝缘材料层（13）并在所述绝缘层上淀积一层导电材料（14），b） 绝缘栅电极（INS-G），从所述重叠绝缘层（13）和导电层（14）开始，其特征在于还包括以下步骤：c）从所述重叠绝缘层（13）和 导电（14）层，布置在第一有源区（D-REG）的第一表面部分（N阱）上的附加结构（ADD-STR），d）放置在绝缘栅电极（INS-G）和 附加结构（ADD-STR）放置在第一有源区（D-REG）的第二表面部分（17）上的电介质间隔物（C-SP）。

公开(公告)号：EP1321985B1

公开(公告)日：2007-10-24

申请号：EP01830786.8

申请日：2001-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Alessandro ,  Croce, Giuseppe

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A metal oxide semiconductor transistor (200) integrated in a wafer of semiconductor material (30) and comprising a gate structure (3, 11) located on a surface of the said wafer and including a gate oxide layer (3). The transistor (200) is characterized in that the said gate oxide layer (3) includes a first portion (4) having a first thickness (t1) and a second portion (5) having a second thickness (t2) differing from the first thickness.

公开(公告)号：EP1321985A1

公开(公告)日：2003-06-25

申请号：EP01830786.8

申请日：2001-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Moscatelli, Alessandro ,  Croce, Giuseppe

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A metal oxide semiconductor transistor (200) integrated in a wafer of semiconductor material (30) and comprising a gate structure (3, 11) located on a surface of the said wafer and including a gate oxide layer (3). The transistor (200) is characterized in that the said gate oxide layer (3) includes a first portion (4) having a first thickness (t1) and a second portion (5) having a second thickness (t2) differing from the first thickness.

Abstract translation: 一种金属氧化物半导体晶体管（200），其集成在半导体材料（30）的晶片中，并且包括位于所述晶片的表面上并包括栅极氧化物层（3）的栅极结构（3,11）。 晶体管（200）的特征在于，所述栅极氧化物层（3）包括具有第一厚度（t1）的第一部分（4）和具有与第一厚度不同的第二厚度（t2）的第二部分（5） 。