公开(公告)号：WO2007006505A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006673

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity forming the drain epitaxial layer (20) on the semiconductor substrate (100) , forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step forming second sub-regions (Dl, DIa) of the first type of conductivity by means of a second implant step forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51) , carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成有漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤：至少形成 在所述半导体衬底（100）上形成所述漏极外延层（20）的所述第一导电类型的第一半导体外延层（21），通过第一选择性形成第二导电类型的第一子区域（51） 植入步骤通过形成表面半导体层（23）的第二注入步骤形成第一类型导电性的第二子区域（D1，DIa），其中形成第二导电类型的主体区域（40）与 所述第一子区域（51）进行热扩散处理，使得所述第一子区域（51）形成与所述主体区域（40）电接触的单个电连续列区域（50）。

公开(公告)号：WO2007006506A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006674

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10) comprising a superficial semiconductor layer (11), the method comprising the steps of: forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) carrying out at least a first ion implantation of a first type of dopant for forming at least one deep implanted region (14a); carrying out at least a second ion implantation of the first type of dopant for forming at least one body region (16) of the MOS transistor aligned with the deep implanted region (14a); the method comprising an activation thermal process with 1-14 low thermal budget of the first type and second type of dopant suitable to complete said formation of the body region (16), and of the deep implanted region (14a).

Abstract translation: 在宽带隙半导体衬底（10）上制造垂直功率MOS晶体管的方法，包括表面半导体层（11），所述方法包括以下步骤：在所述表面半导体层（11）上形成屏蔽结构（12），包括： 至少一个电介质层（12）至少执行用于形成至少一个深注入区域（14a）的第一类型掺杂剂的第一离子注入; 执行所述第一类型掺杂剂的至少第二离子注入以形成与所述深注入区域（14a）对准的所述MOS晶体管的至少一个体区（16）。 该方法包括具有适合于完成所述体区（16）的所述第一类型和第二类型掺杂物的1-14低热预算的激活热处理以及所述深注入区域（14a）。

公开(公告)号：WO2007122646A1

公开(公告)日：2007-11-01

申请号：PCT/IT2006/000273

申请日：2006-04-21

Applicant: STMICROELECTRONICS S.R.L. ,  GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： GUARNERA, Alfio ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/10 ,  H01L29/739 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/0634 ,  H01L21/2003 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a power semiconductor device (25; 35) envisages the steps of: providing a body of semiconductor material (3) having a top surface (4) and having a first conductivity; forming columnar regions (6) having a second type of conductivity within the body of semiconductor material (3), and surface extensions (10) of the columnar regions (6) above the top surface (4); and forming doped regions (19, 20) having the second type of conductivity, in the proximity of the top surface (4) and in contact with the columnar regions (6). The doped regions (19, 20) are formed at least partially within the surface extensions (10) of the columnar regions (6); the surface extensions (10) and the doped regions (20) have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract translation: 一种用于制造功率半导体器件（25; 35）的工艺设想了以下步骤：提供具有顶表面（4）并具有第一导电性的半导体材料体（3）; 在所述半导体材料（3）的主体内形成具有第二导电类型的柱状区域（6）以及所述顶表面（4）上方的所述柱状区域（6）的表面延伸部（10）。 以及在所述顶表面（4）附近形成具有所述第二导电类型的掺杂区域（19,20）并与所述柱状区域（6）接触。 掺杂区域（19,20）至少部分地形成在柱状区域（6）的表面延伸部分（10）内; 表面延伸部（10）和掺杂区域（20）具有非平面的表面图案，特别是具有大致V形的凹槽。

公开(公告)号：WO2006089725A3

公开(公告)日：2006-08-31

申请号：PCT/EP2006/001591

申请日：2006-02-22

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/78

Abstract: Power semiconductor device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), and a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlying each other, the resistivity of each layer being different from that of the other layers, and wherein said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24).

公开(公告)号：WO2007006507A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006675

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a semiconductor substrate (10) with wide band gap comprising a first superficial semiconductor layer (11) with wide band gap of a first type of conductivity, comprising the steps of: forming trench regions (13) in the first superficial semiconductor layer (H), filling in said trench regions (13) by means of a second semiconductor layer (14) with wide band gap of a second type of conductivity, so as to form semiconductor portions (15) of the second type of conductivity contained in the first superficial semiconductor layer (11), carrying out at least one ion implantation of a first type of dopant in the semiconductor portions (15) for forming respective implanted body regions (19) of said second type of conductivity, carrying out at least one ion implantation of a second type of dopant in each of the implanted body regions (19) for forming at least one implanted source region (23) of the first type of conductivity inside the implanted body regions (19), carrying out an activation thermal process of the first and second type of dopant with low thermal budget suitable to complete said formation of the implanted body and source regions (19, 23).

Abstract translation: 一种用于制造具有宽带隙的半导体衬底（10）上的垂直功率MOS晶体管的方法，包括具有第一类型导电性的宽带隙的第一表面半导体层（11），包括以下步骤：形成沟槽区域（13） 在第一表面半导体层（H）中，通过具有第二导电类型的宽带隙的第二半导体层（14）填充所述沟槽区域（13），以形成第二半导体层 在第一表面半导体层（11）中包含的第二类导电体，在半导体部分（15）中进行至少一种第一类型掺杂剂的离子注入，用于形成所述第二导电类型的各个植入体区域（19） 在每个植入体区域（19）中进行至少一个第二类型掺杂剂的离子注入，用于在im内形成至少一个第一类型的电导率的注入源区（23） 植入体区域（19），以适合于完成植入体和源区（19,23）的所述形成的低热预算进行第一和第二类型掺杂剂的活化热处理。

公开(公告)号：WO2007006503A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006671

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).

Abstract translation: 一种用于制造功率电子器件（30）的方法，包括以下步骤：形成第一类型的导电性的第一半导体层（21），其形成至少第二类型的电导率值的第二半导体层（22），其在第一半导体 在所述至少第二半导体层（22）中形成所述第一类型的导电形成的第一多个注入区域（D1），在所述至少第二半导体层（22）之上，表面（21），表面 在所述表面半导体层（26）中形成所述第一导电类型的半导体层（26），所述半导体层（26）在所述第二导电类型的主体区域（40）中形成，所述主体区域（40）与半导体层 从所述多个所述至少第二注入区域（D1）中，进行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续的注入区域（D）。

公开(公告)号：WO2007116420A1

公开(公告)日：2007-10-18

申请号：PCT/IT2006/000244

申请日：2006-04-11

Applicant: STMICROELECTRONICS S.R.L. ,  LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/10 ,  H01L29/739 ,  H01L29/732

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench (8) is formed in a semiconductor body (2) having a first conductivity type; the trench is annealed for shaping purpose (8a) ; and the trench (8a) is filled with semiconductor material via epitaxial growth so as to obtain a first column (9) having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases .

Abstract translation: 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体（2）中形成沟槽（8） 沟槽退火成型目的（8a）; 并且沟槽（8a）通过外延生长填充半导体材料，从而获得具有第二导电类型的第一列（9）。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：WO2007006504A3

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006672

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1, 1a; 10, 11) with wide band gap comprising the steps of: forming a screening structure (3a, 20) on said semiconductor substrate (1, 1a; 10, 11) comprising at least a dielectric layer (2, 20) which leaves a plurality of areas of said semiconductor substrate (1, 1a; 10, 11) exposed, carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a first implanted region (4, 40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a second implanted region (6, 6c; 60, 61) inside said at least a first implanted region (4, 40), carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4, 40; 6, 60).

公开(公告)号：EP1210752B1

公开(公告)日：2004-11-24

申请号：EP00975849.1

申请日：2000-09-01

Applicant: STMicroelectronics S.r.l.

Inventor： COFFA, Salvatore ,  LIBERTINO, Sebania ,  SAGGIO, Mario ,  FRISINA, Ferruccio

IPC: H01S3/16 ,  H01S5/32

CPC classification number: H01S5/305 ,  H01S3/1603 ,  H01S3/1628 ,  H01S5/3004 ,  H01S5/3068

Abstract: The invention relates to a semiconductor device for electro-optic applications of the type including at least a rare-earth ions doped P/N junction integrated on a semiconductor substrate. This device may be used to obtain laser action in Silicon and comprises a cavity or a waveguide and a coherent light source obtained incorporating the rare-earth ions, and specifically Erbium ions, in the depletion layer of said P/N junction. The junction may be for instance the base-collector region of a bipolar transistor and is reverse biased.

公开(公告)号：EP1908096A1

公开(公告)日：2008-04-09

申请号：EP06762483.3

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate (10,11) comprising a wide band gap superficial semiconductor layer (11), the method comprising the steps of: - forming a screening structure (12) on the superficial semiconductor layer (11) comprising at least one dielectric layer (12) which leaves a plurality of areas of the superficial semiconductor layer (11) exposed, - carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer (11) for forming at least one deep implanted region (14a), - carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer (11) for forming at least one implanted body region (16) of the MOS transistor aligned with the deep implanted region (14a), - carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer (11) for forming at least an implanted source region (18) of the MOS transistor inside the at least one implanted body region (16), the method comprising an activation thermal process of the first type and second type of low thermal budget dopant suitable to complete said formation of the body region (16), of the source region (18) and of the deep implanted region (14a).